From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A672DC433F5 for ; Fri, 17 Dec 2021 18:45:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NNTgye36+HfqqRXHgezYldKz0f1gIoP23HcrEW7eB9g=; b=wSVSagD3I4FEr1 9xAevEnvdtb7JbtK30966k4NQm1FWHKncLKcnwzqwQhytfxgPngS3He+Ia2rs6j8DbuxAGBepBSQ4 EkBPElUNSDBG0ptDjAKLmqFp27CW1xXvCGLZR8Z0VPfgTSJCH2nQKIM5N2/qs0T9uq7szSoOef+jX C8Qj2kNXJoy8GQNXLJzVDl2WaiRl6nJAYVgBdYmJegepXeBaRjo+L7W1JZ/qLvVx1pqKLt7//G99x 2BeDtGt4rbK1KtLuAbwXmkqdTlA7rbgc37zGu4tkGJvTqu+pY7PrKb1+My0vduPT8rYiUrL7lIkDc uoHYB7WGraRFvezMEHGQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1myID6-00BwiE-UY; Fri, 17 Dec 2021 18:44:06 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myHmv-00BkTR-Un for linux-arm-kernel@lists.infradead.org; Fri, 17 Dec 2021 18:17:03 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 621286236C; Fri, 17 Dec 2021 18:17:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 74597C36AE1; Fri, 17 Dec 2021 18:16:59 +0000 (UTC) Date: Fri, 17 Dec 2021 18:16:56 +0000 From: Catalin Marinas To: Peter Collingbourne Cc: Vincenzo Frascino , Will Deacon , Andrey Konovalov , Mark Rutland , Evgenii Stepanov , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2] arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary Message-ID: References: <20211110220735.3937127-1-pcc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_101702_074022_DE091E85 X-CRM114-Status: GOOD ( 26.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Dec 15, 2021 at 06:44:03PM -0800, Peter Collingbourne wrote: > On Fri, Dec 10, 2021 at 4:06 AM Catalin Marinas wrote: > > On Wed, Nov 10, 2021 at 02:07:35PM -0800, Peter Collingbourne wrote: > > > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > > > index 2f69ae43941d..a78ec15f5bbc 100644 > > > --- a/arch/arm64/kernel/entry.S > > > +++ b/arch/arm64/kernel/entry.S > > > @@ -189,6 +189,27 @@ alternative_cb_end > > > #endif > > > .endm > > > > > > + .macro mte_clear_tco, sctlr > > > + /* > > > + * Re-enable tag checking (TCO set on exception entry). This is only > > > + * necessary if MTE is enabled in either the kernel or the userspace > > > + * task in synchronous mode. With MTE disabled in the kernel and > > > + * disabled or asynchronous in userspace, tag check faults (including in > > > + * uaccesses) are not reported, therefore there is no need to re-enable > > > + * checking. This is beneficial on microarchitectures where re-enabling > > > + * TCO is expensive. > > > + */ > > > +#ifdef CONFIG_ARM64_MTE > > > +alternative_cb kasan_hw_tags_enable > > > + tbz \sctlr, #SCTLR_EL1_TCF0_SHIFT, 1f > > > +alternative_cb_end > > > +alternative_if ARM64_MTE > > > + SET_PSTATE_TCO(0) > > > +alternative_else_nop_endif > > > +1: > > > +#endif > > > + .endm > > > > The patch looks fine to me but I recall in a private conversation with > > Mark he proposed the idea of moving this to entry-common.c (unless it > > was about something completely different). The downside is that we run > > with the TCO set for slightly longer. There shouldn't be a major > > drawback currently as we don't have stack tagging anyway. > > Yes, Mark made that suggestion on the list. I tried it and found that > it led to a performance regression relative to baseline [1]. [...] > [1] https://lore.kernel.org/all/CAMn1gO51k1Dqts=THYq28nVMSvO6ZQB5sEG1wuzEVpAXBTfFjg@mail.gmail.com/ That's weird since there should be the same number of instructions executed on entry with your diff above. Could it be that mte_disable_tco_entry() is not inlined? -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel