From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E844C433EF for ; Tue, 25 Jan 2022 05:17:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AEDA910E2DF; Tue, 25 Jan 2022 05:17:33 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id A1AA410E2F4; Tue, 25 Jan 2022 05:17:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643087852; x=1674623852; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=szMhn+GZucHPTDtHBcqaEh1jiwyMxWJmIcgFkQpSSbQ=; b=OaUH3Gr7tRwXXkRd3UTj6vOpewleXmaXs0qOmUJU8MI61wU4khd9jxXy 3HGerIXEsGHSmW/3yq079Hdmex6Ej7OVVaUt+lYpg5WdY5mR2/v4GMxRn eFPGo9JetxyfEtQYJrowf8r2EFv1xFLi0zp3Ve3qpxZCFXy6OtVw4ezFT Q4JPMtpAICecsWt/DYEcYkU2FRLa3vzhlU/UN1Tr/upo++Zf9lLBJMB4d ncAk/Sp4X2uW154o0xtkKrT/llXTSKNM42q0YQscaNyabih1aj/Q5UJzt AWqdeEqy9beIY9CwfY3pZqMAddUJl96Ug3HaS227UAPCS+5622+Len9l8 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10237"; a="246004088" X-IronPort-AV: E=Sophos;i="5.88,314,1635231600"; d="scan'208";a="246004088" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2022 21:17:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,314,1635231600"; d="scan'208";a="624343984" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.147]) by fmsmga002.fm.intel.com with SMTP; 24 Jan 2022 21:17:26 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 25 Jan 2022 07:17:25 +0200 Date: Tue, 25 Jan 2022 07:17:25 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Dan Carpenter Message-ID: References: <20220124122409.GA31673@kili> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220124122409.GA31673@kili> X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH] drm/i915/overlay: Prevent divide by zero bugs in scaling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , kernel-janitors@vger.kernel.org, intel-gfx@lists.freedesktop.org, Chris Wilson , Eric Anholt , Sean Paul , dri-devel@lists.freedesktop.org, Fernando Ramos Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, Jan 24, 2022 at 03:24:09PM +0300, Dan Carpenter wrote: > Smatch detected a divide by zero bug in check_overlay_scaling(). > > drivers/gpu/drm/i915/display/intel_overlay.c:976 check_overlay_scaling() > error: potential divide by zero bug '/ rec->dst_height'. > drivers/gpu/drm/i915/display/intel_overlay.c:980 check_overlay_scaling() > error: potential divide by zero bug '/ rec->dst_width'. > > Prevent this by ensuring that the dst height and width are non-zero. > > Fixes: 02e792fbaadb ("drm/i915: implement drmmode overlay support v4") > Signed-off-by: Dan Carpenter Thanks. Pushed to drm-intel-next. > --- > >From static analysis. Not tested. > > drivers/gpu/drm/i915/display/intel_overlay.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c > index 1a376e9a1ff3..d610e48cab94 100644 > --- a/drivers/gpu/drm/i915/display/intel_overlay.c > +++ b/drivers/gpu/drm/i915/display/intel_overlay.c > @@ -959,6 +959,9 @@ static int check_overlay_dst(struct intel_overlay *overlay, > const struct intel_crtc_state *pipe_config = > overlay->crtc->config; > > + if (rec->dst_height == 0 || rec->dst_width == 0) > + return -EINVAL; > + > if (rec->dst_x < pipe_config->pipe_src_w && > rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && > rec->dst_y < pipe_config->pipe_src_h && > -- > 2.20.1 -- Ville Syrjälä Intel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86EB1C433FE for ; Tue, 25 Jan 2022 05:55:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241119AbiAYFzb (ORCPT ); Tue, 25 Jan 2022 00:55:31 -0500 Received: from mga04.intel.com ([192.55.52.120]:21601 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229667AbiAYF3h (ORCPT ); Tue, 25 Jan 2022 00:29:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643088577; x=1674624577; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=szMhn+GZucHPTDtHBcqaEh1jiwyMxWJmIcgFkQpSSbQ=; b=JUrRQvlEErBUiJx4Eulam1oi85Wi9ulHMC/5TBrUC5XXPD5reL4TDfWr BpZxTOCAJ+b5Nqnl0F6DliCV9ArxDAy0xxPkMYjPwJk3fFbDJwKVDPj1G mTqfgtMdG5mh5xY9luELc/Jw39tQpjtyhBrDO2otuBFUnBoLTgfVwg7qT Ab+IRhjXIcvQeNlEvuD27fUtcUzoRHGSXUyrgKL/tNK9AbK/fH10CCH8e RYmgjArU9rIluL23qZyfJ0aV9Y5KHCpJ6oiV2UW/OOqMZ4ySl5JJUYgba Skru88DW2j6+TvWyJKxgedTHhMhPvB+Fg799AFAg8EI5YGti1vELBoIQK Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10237"; a="245056447" X-IronPort-AV: E=Sophos;i="5.88,314,1635231600"; d="scan'208";a="245056447" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2022 21:17:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,314,1635231600"; d="scan'208";a="624343984" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.147]) by fmsmga002.fm.intel.com with SMTP; 24 Jan 2022 21:17:26 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 25 Jan 2022 07:17:25 +0200 Date: Tue, 25 Jan 2022 07:17:25 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Dan Carpenter Cc: Jani Nikula , Daniel Vetter , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Chris Wilson , Sean Paul , Fernando Ramos , Maarten Lankhorst , Matt Roper , Eric Anholt , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, kernel-janitors@vger.kernel.org Subject: Re: [PATCH] drm/i915/overlay: Prevent divide by zero bugs in scaling Message-ID: References: <20220124122409.GA31673@kili> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220124122409.GA31673@kili> X-Patchwork-Hint: comment Precedence: bulk List-ID: X-Mailing-List: kernel-janitors@vger.kernel.org On Mon, Jan 24, 2022 at 03:24:09PM +0300, Dan Carpenter wrote: > Smatch detected a divide by zero bug in check_overlay_scaling(). > > drivers/gpu/drm/i915/display/intel_overlay.c:976 check_overlay_scaling() > error: potential divide by zero bug '/ rec->dst_height'. > drivers/gpu/drm/i915/display/intel_overlay.c:980 check_overlay_scaling() > error: potential divide by zero bug '/ rec->dst_width'. > > Prevent this by ensuring that the dst height and width are non-zero. > > Fixes: 02e792fbaadb ("drm/i915: implement drmmode overlay support v4") > Signed-off-by: Dan Carpenter Thanks. Pushed to drm-intel-next. > --- > >From static analysis. Not tested. > > drivers/gpu/drm/i915/display/intel_overlay.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c > index 1a376e9a1ff3..d610e48cab94 100644 > --- a/drivers/gpu/drm/i915/display/intel_overlay.c > +++ b/drivers/gpu/drm/i915/display/intel_overlay.c > @@ -959,6 +959,9 @@ static int check_overlay_dst(struct intel_overlay *overlay, > const struct intel_crtc_state *pipe_config = > overlay->crtc->config; > > + if (rec->dst_height == 0 || rec->dst_width == 0) > + return -EINVAL; > + > if (rec->dst_x < pipe_config->pipe_src_w && > rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && > rec->dst_y < pipe_config->pipe_src_h && > -- > 2.20.1 -- Ville Syrjälä Intel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB925C433EF for ; Tue, 25 Jan 2022 05:17:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EBBF210E311; Tue, 25 Jan 2022 05:17:33 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id A1AA410E2F4; Tue, 25 Jan 2022 05:17:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643087852; x=1674623852; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=szMhn+GZucHPTDtHBcqaEh1jiwyMxWJmIcgFkQpSSbQ=; b=OaUH3Gr7tRwXXkRd3UTj6vOpewleXmaXs0qOmUJU8MI61wU4khd9jxXy 3HGerIXEsGHSmW/3yq079Hdmex6Ej7OVVaUt+lYpg5WdY5mR2/v4GMxRn eFPGo9JetxyfEtQYJrowf8r2EFv1xFLi0zp3Ve3qpxZCFXy6OtVw4ezFT Q4JPMtpAICecsWt/DYEcYkU2FRLa3vzhlU/UN1Tr/upo++Zf9lLBJMB4d ncAk/Sp4X2uW154o0xtkKrT/llXTSKNM42q0YQscaNyabih1aj/Q5UJzt AWqdeEqy9beIY9CwfY3pZqMAddUJl96Ug3HaS227UAPCS+5622+Len9l8 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10237"; a="246004088" X-IronPort-AV: E=Sophos;i="5.88,314,1635231600"; d="scan'208";a="246004088" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2022 21:17:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,314,1635231600"; d="scan'208";a="624343984" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.147]) by fmsmga002.fm.intel.com with SMTP; 24 Jan 2022 21:17:26 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 25 Jan 2022 07:17:25 +0200 Date: Tue, 25 Jan 2022 07:17:25 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Dan Carpenter Subject: Re: [PATCH] drm/i915/overlay: Prevent divide by zero bugs in scaling Message-ID: References: <20220124122409.GA31673@kili> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220124122409.GA31673@kili> X-Patchwork-Hint: comment X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , David Airlie , kernel-janitors@vger.kernel.org, intel-gfx@lists.freedesktop.org, Chris Wilson , Eric Anholt , Sean Paul , dri-devel@lists.freedesktop.org, Rodrigo Vivi , Fernando Ramos Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, Jan 24, 2022 at 03:24:09PM +0300, Dan Carpenter wrote: > Smatch detected a divide by zero bug in check_overlay_scaling(). > > drivers/gpu/drm/i915/display/intel_overlay.c:976 check_overlay_scaling() > error: potential divide by zero bug '/ rec->dst_height'. > drivers/gpu/drm/i915/display/intel_overlay.c:980 check_overlay_scaling() > error: potential divide by zero bug '/ rec->dst_width'. > > Prevent this by ensuring that the dst height and width are non-zero. > > Fixes: 02e792fbaadb ("drm/i915: implement drmmode overlay support v4") > Signed-off-by: Dan Carpenter Thanks. Pushed to drm-intel-next. > --- > >From static analysis. Not tested. > > drivers/gpu/drm/i915/display/intel_overlay.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c > index 1a376e9a1ff3..d610e48cab94 100644 > --- a/drivers/gpu/drm/i915/display/intel_overlay.c > +++ b/drivers/gpu/drm/i915/display/intel_overlay.c > @@ -959,6 +959,9 @@ static int check_overlay_dst(struct intel_overlay *overlay, > const struct intel_crtc_state *pipe_config = > overlay->crtc->config; > > + if (rec->dst_height == 0 || rec->dst_width == 0) > + return -EINVAL; > + > if (rec->dst_x < pipe_config->pipe_src_w && > rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && > rec->dst_y < pipe_config->pipe_src_h && > -- > 2.20.1 -- Ville Syrjälä Intel