Re: [PATCH 1/3] drm/amdgpu: convert to NBIO IP version checking

[Huang Rui <ray.huang@amd.com>]

On Mon, Jan 24, 2022 at 11:20:40AM +0800, Huang, Tim wrote:
> Use IP versions rather than asic_type to differentiate IP version specific features.
> 
> Signed-off-by: Tim Huang <xiaohu.huang@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 48 ++++++++++++++++++--------
>  1 file changed, 34 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> index 3444332ea110..70e341d884d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> @@ -59,10 +59,15 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
>  
> -	if (adev->asic_type == CHIP_YELLOW_CARP)
> +	switch (adev->ip_versions[NBIO_HWIP][0]) {
> +	case IP_VERSION(7, 2, 1):
> +	case IP_VERSION(7, 5, 0):
>  		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
> -	else
> +		break;
> +	default:
>  		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
> +		break;
> +	}
>  
>  	tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
>  	tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
> @@ -72,20 +77,25 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
>  
>  static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
>  {
> -	if (enable)
> -		if (adev->asic_type == CHIP_YELLOW_CARP)
> +	switch (adev->ip_versions[NBIO_HWIP][0]) {
> +	case IP_VERSION(7, 2, 1):
> +	case IP_VERSION(7, 5, 0):
> +		if (enable)
>  			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
>  				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
>  				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
>  		else
> +			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
> +	break;
> +	default:
> +		if (enable)
>  			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
>  				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
>  				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
> -	else
> -		if (adev->asic_type == CHIP_YELLOW_CARP)
> -			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
>  		else
>  			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
> +		break;
> +	}
>  }
>  
>  static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
> @@ -249,8 +259,10 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>  						      bool enable)
>  {
>  	uint32_t def, data;
> -
> -	if (adev->asic_type == CHIP_YELLOW_CARP) {
> +	
> +	switch (adev->ip_versions[NBIO_HWIP][0]) {
> +	case IP_VERSION(7, 2, 1):
> +	case IP_VERSION(7, 5, 0):
>  		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
>  		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
>  			data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
> @@ -260,8 +272,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
>  
> -		data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1));
> -		def = data;
> +		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
> +			regBIF1_PCIE_TX_POWER_CTRL_1));
>  		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
>  			data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
>  				BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
> @@ -272,7 +284,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
>  				data);
> -	} else {
> +		break;
> +	default:
>  		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
>  		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
>  			data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
> @@ -285,6 +298,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>  
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
> +
> +		break;
>  	}
>  }
>  
> @@ -352,7 +367,9 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
>  static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>  {
>  	uint32_t def, data;
> -	if (adev->asic_type == CHIP_YELLOW_CARP) {
> +	switch (adev->ip_versions[NBIO_HWIP][0]) {
> +	case IP_VERSION(7, 2, 1):
> +	case IP_VERSION(7, 5, 0):
>  		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
>  		data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
>  			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
> @@ -361,7 +378,8 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>  
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
> -	} else {
> +		break;
> +	default:
>  		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
>  		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
>  			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
> @@ -370,6 +388,8 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>  
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
> +
> +		break;
>  	}
>  
>  	if (amdgpu_sriov_vf(adev))
> -- 
> 2.25.1
>