From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DA93C433EF for ; Mon, 24 Jan 2022 11:46:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uMX5XRAn1ZYHcEy2Ndnwxd8fZ26dxYEyVSAeW2HCjD8=; b=gyL8pR79JLLIt+ U6/Lu7WWwqvSq+qEQnqHGv85V0PCXynx/6MGVvMRHglORBsDBq7v0oZu7/uXv41E2xF0m3EmTFw0u Jy8ltpVAS4GcRPmIxSgtD0j/yHHWm1aSW7sxPQfudjGGOPnu5LQVCG6//1aq8conNMJx2glJofeI+ OxKmVljfV8y9o4xQqBe8vyVZ3D45PsPmo9IEe9ri2qDl6LuH2XA1qkkLmi1CsmAr5Gf5uic0X7b1h 88cifm32bL6uFU7HPFtcHMcOEQQfSXN2+7RrNpkwf+tWauP8dZbEJdNSSYjTrJ5xPCSv83CPrJPbN AKlyR1qGGOCN6NHg5AHg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nBxmo-0036EZ-AL; Mon, 24 Jan 2022 11:45:26 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nBxmj-0036Do-W1 for linux-arm-kernel@lists.infradead.org; Mon, 24 Jan 2022 11:45:23 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A1F37B80EF1; Mon, 24 Jan 2022 11:45:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B731FC340E1; Mon, 24 Jan 2022 11:45:17 +0000 (UTC) Date: Mon, 24 Jan 2022 11:45:14 +0000 From: Catalin Marinas To: Peter Collingbourne Cc: Vincenzo Frascino , Will Deacon , Andrey Konovalov , Mark Rutland , Evgenii Stepanov , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3] arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary Message-ID: References: <20220122010250.251885-1-pcc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220122010250.251885-1-pcc@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220124_034522_201089_F38F30B8 X-CRM114-Status: GOOD ( 24.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jan 21, 2022 at 05:02:50PM -0800, Peter Collingbourne wrote: > diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h > index 075539f5f1c8..5352db4c0f45 100644 > --- a/arch/arm64/include/asm/mte.h > +++ b/arch/arm64/include/asm/mte.h > @@ -11,7 +11,9 @@ > #ifndef __ASSEMBLY__ > > #include > +#include > #include > +#include > #include > > #include > @@ -86,6 +88,23 @@ static inline int mte_ptrace_copy_tags(struct task_struct *child, > > #endif /* CONFIG_ARM64_MTE */ > > +static inline void mte_disable_tco_entry(struct task_struct *task) > +{ > + /* > + * Re-enable tag checking (TCO set on exception entry). This is only > + * necessary if MTE is enabled in either the kernel or the userspace > + * task in synchronous mode. With MTE disabled in the kernel and > + * disabled or asynchronous in userspace, tag check faults (including in > + * uaccesses) are not reported, therefore there is no need to re-enable > + * checking. This is beneficial on microarchitectures where re-enabling > + * TCO is expensive. > + */ I'd add a note here that the 1ULL << SCTLR_EL1_TCF0_SHIFT is meant to check for both synchronous and asymmetric modes even if we don't have the latter supporting the user yet. We do have the definitions already. > + if (kasan_hw_tags_enabled() || > + (system_supports_mte() && > + (task->thread.sctlr_user & (1UL << SCTLR_EL1_TCF0_SHIFT)))) > + asm volatile(SET_PSTATE_TCO(0)); > +} Does it make a difference in code generation if you place a: if (!system_supports_mte()) return; at the beginning of the function (and remove the subsequent check)? It's probably also easier to read, though the code generation depends on the likely/unlikely choices for the static branches involved. > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > index f418ebc65f95..5345587f3384 100644 > --- a/arch/arm64/kernel/mte.c > +++ b/arch/arm64/kernel/mte.c > @@ -252,6 +252,7 @@ void mte_thread_switch(struct task_struct *next) > > mte_update_sctlr_user(next); > mte_update_gcr_excl(next); > + mte_disable_tco_entry(next); Maybe a one-line comment here that TCO may not have been disabled on exception entry for the current task. Otherwise it looks good to me: Reviewed-by: Catalin Marinas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel