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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id x1sm1277327oto.38.2022.02.04.15.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 15:02:33 -0800 (PST) Received: (nullmailer pid 3346874 invoked by uid 1000); Fri, 04 Feb 2022 23:02:32 -0000 Date: Fri, 4 Feb 2022 17:02:32 -0600 From: Rob Herring To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Thomas Gleixner , Dougall , kernel-team@android.com Subject: Re: [PATCH v4 03/10] dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts Message-ID: References: <20220124201231.298961-1-maz@kernel.org> <20220124201231.298961-4-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220124201231.298961-4-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220204_150235_532828_988793AE X-CRM114-Status: GOOD ( 20.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jan 24, 2022 at 08:12:24PM +0000, Marc Zyngier wrote: > Some of the FIQ per-cpu pseudo-interrupts are better described with > a specific affinity, the most obvious candidate being the CPU PMUs. > > Augment the AIC binding to be able to specify that affinity in the > interrupt controller node. > > Signed-off-by: Marc Zyngier > --- > .../interrupt-controller/apple,aic.yaml | 27 +++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > index c7577d401786..d97683eb2c54 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > @@ -70,6 +70,33 @@ properties: > power-domains: > maxItems: 1 > > + affinities: > + type: object additionalProperties: false > + description: > + FIQ affinity can be expressed as a single "affinities" node, > + containing a set of sub-nodes, one per FIQ with a non-default > + affinity. > + patternProperties: > + "^.+-affinity$": > + type: object additionalProperties: false > + properties: > + fiq-index: apple,fiq-index With that, Reviewed-by: Rob Herring > + description: > + The interrupt number specified as a FIQ, and for which > + the affinity is not the default. > + $ref: /schemas/types.yaml#/definitions/uint32 > + maximum: 5 > + > + cpus: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Should be a list of phandles to CPU nodes (as described in > + Documentation/devicetree/bindings/arm/cpus.yaml). > + > + required: > + - fiq-index > + - cpus > + > required: > - compatible > - '#interrupt-cells' > -- > 2.30.2 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18B07C433EF for ; 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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id x1sm1277327oto.38.2022.02.04.15.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 15:02:33 -0800 (PST) Received: (nullmailer pid 3346874 invoked by uid 1000); Fri, 04 Feb 2022 23:02:32 -0000 Date: Fri, 4 Feb 2022 17:02:32 -0600 From: Rob Herring To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Thomas Gleixner , Dougall , kernel-team@android.com Subject: Re: [PATCH v4 03/10] dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts Message-ID: References: <20220124201231.298961-1-maz@kernel.org> <20220124201231.298961-4-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220124201231.298961-4-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Jan 24, 2022 at 08:12:24PM +0000, Marc Zyngier wrote: > Some of the FIQ per-cpu pseudo-interrupts are better described with > a specific affinity, the most obvious candidate being the CPU PMUs. > > Augment the AIC binding to be able to specify that affinity in the > interrupt controller node. > > Signed-off-by: Marc Zyngier > --- > .../interrupt-controller/apple,aic.yaml | 27 +++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > index c7577d401786..d97683eb2c54 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml > @@ -70,6 +70,33 @@ properties: > power-domains: > maxItems: 1 > > + affinities: > + type: object additionalProperties: false > + description: > + FIQ affinity can be expressed as a single "affinities" node, > + containing a set of sub-nodes, one per FIQ with a non-default > + affinity. > + patternProperties: > + "^.+-affinity$": > + type: object additionalProperties: false > + properties: > + fiq-index: apple,fiq-index With that, Reviewed-by: Rob Herring > + description: > + The interrupt number specified as a FIQ, and for which > + the affinity is not the default. > + $ref: /schemas/types.yaml#/definitions/uint32 > + maximum: 5 > + > + cpus: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Should be a list of phandles to CPU nodes (as described in > + Documentation/devicetree/bindings/arm/cpus.yaml). > + > + required: > + - fiq-index > + - cpus > + > required: > - compatible > - '#interrupt-cells' > -- > 2.30.2 > >