Re: [PATCH v3 2/5] clk: qcom: gcc-msm8998: add SSC-related clocks

[Bjorn Andersson <bjorn.andersson@linaro.org>]

On Mon 24 Jan 06:18 CST 2022, michael.srba@seznam.cz wrote:

> From: Michael Srba <Michael.Srba@seznam.cz>
> 
>  This patch adds four clocks which need to be manipulated in order to

Please skip the space on the start of each line here.

>  initialize the AHB bus which exposes the SCC block in the global address
>  space.
> 
>  Care should be taken not to write to these registers unless the device is
>  known to be configured such that writing to these registers from Linux
>  is permitted.

Does this imply that applying this will break the existing devices and
care _must_ be taken, presumably before we can apply the patch?

Regards,
Bjorn

> 
> Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
> ---
>  CHANGES:
>  - v2: none
>  - v3: none
> ---
>  drivers/clk/qcom/gcc-msm8998.c | 56 ++++++++++++++++++++++++++++++++++
>  1 file changed, 56 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
> index 407e2c5caea4..2d14c3d672fc 100644
> --- a/drivers/clk/qcom/gcc-msm8998.c
> +++ b/drivers/clk/qcom/gcc-msm8998.c
> @@ -2833,6 +2833,58 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
>  	},
>  };
>  
> +static struct clk_branch gcc_im_sleep_clk = {
> +	.halt_reg = 0x4300C,
> +	.halt_check = BRANCH_HALT,
> +	.clkr = {
> +		.enable_reg = 0x4300C,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_im_sleep_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch aggre2_snoc_north_axi_clk = {
> +	.halt_reg = 0x83010,
> +	.halt_check = BRANCH_HALT,
> +	.clkr = {
> +		.enable_reg = 0x83010,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "aggre2_snoc_north_axi_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch ssc_xo_clk = {
> +	.halt_reg = 0x63018,
> +	.halt_check = BRANCH_HALT,
> +	.clkr = {
> +		.enable_reg = 0x63018,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "ssc_xo_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch ssc_cnoc_ahbs_clk = {
> +	.halt_reg = 0x6300C,
> +	.halt_check = BRANCH_HALT,
> +	.clkr = {
> +		.enable_reg = 0x6300C,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "ssc_cnoc_ahbs_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>  static struct gdsc pcie_0_gdsc = {
>  	.gdscr = 0x6b004,
>  	.gds_hw_ctrl = 0x0,
> @@ -3036,6 +3088,10 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
>  	[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
>  	[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
>  	[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
> +	[GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr,
> +	[AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,
> +	[SSC_XO] = &ssc_xo_clk.clkr,
> +	[SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,
>  };
>  
>  static struct gdsc *gcc_msm8998_gdscs[] = {
> -- 
> 2.34.1
>