From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD68CC433EF for ; Thu, 27 Jan 2022 15:27:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YTnon3WblUIjsOL+E6ndn1BcAsFh7CYSiXcJPx8P7j0=; b=Ds06k6aAu7BlHk seDt3U33RFG5hSNgzmMWwPWFPXav4UxpKJ+uoqn+nX24njzRUoX2MbBHjgx4wuQiU2ptYEL/vjGb6 pAMSGMu5Yelz5Cosnu77DimvP6F0YRsmo2kUkK7QZksFJrnP/HZX95GFbf8dM7bYtITXTKR2T4EMx XrJepOZ9Y6oA9/c2N3DQnAsfdAzfO2ruuwtWEe9qW9lmefNu6LmiNGigpPVsmrGmLVi39Z0bWc38y 3c2N1EC22fqY6G/0DGqbYuF/2tMyx5XV6O9XuP1+LDeN24wEFphsiED6eime3G2jntGppbfu6gWeT vuy+fPRoHg1+sLKwfMxQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nD6ex-00GFev-Ht; Thu, 27 Jan 2022 15:26:03 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nD6eu-00GFeH-04 for linux-arm-kernel@lists.infradead.org; Thu, 27 Jan 2022 15:26:01 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8D5B061551; Thu, 27 Jan 2022 15:25:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C8A9C340E8; Thu, 27 Jan 2022 15:25:58 +0000 (UTC) Date: Thu, 27 Jan 2022 15:25:54 +0000 From: Catalin Marinas To: James Morse Cc: linux-arm-kernel@lists.infradead.org, Will Deacon , Suzuki K Poulose , Ard Biesheuvel Subject: Re: [PATCH] arm64: errata: Remove AES hwcap for COMPAT tasks on A57 and A72 Message-ID: References: <20220127122914.1585008-1-james.morse@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220127122914.1585008-1-james.morse@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220127_072600_142590_3D721CBC X-CRM114-Status: GOOD ( 26.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi James, On Thu, Jan 27, 2022 at 12:29:14PM +0000, James Morse wrote: > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 9e1c1aef9ebd..b06fb054e055 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -376,6 +376,14 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { > }; > #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ > > +#ifdef CONFIG_ARM64_ERRATUM_1742098 > +static struct midr_range broken_aarch32_aes[] = { > + MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), > + {}, > +}; > +#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ > + > const struct arm64_cpu_capabilities arm64_errata[] = { > #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE > { > @@ -597,6 +605,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), > }, > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_1742098 > + { > + .desc = "ARM erratum 1742098", > + .capability = ARM64_WORKAROUND_1742098, > + CAP_MIDR_RANGE_LIST(broken_aarch32_aes), > + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, > + .cpu_enable = arm64_remove_aes_compat_hwcap, > + }, > #endif > { > } > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index a46ab3b1c4d5..06605e267ab0 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1900,6 +1900,29 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) > } > #endif /* CONFIG_ARM64_MTE */ > > +#ifdef CONFIG_ARM64_ERRATUM_1742098 > +/* > + * compat_elf_hwcap{,2} are built from the sanitised id registers after the > + * enable calls have run. See the order of the setup_system_capabilities() > + * and setup_elf_hwcaps() calls in setup_cpu_features(). Removing the AES > + * field prevents the AES hwcap from being advertised. > + */ > +void arm64_remove_aes_compat_hwcap(const struct arm64_cpu_capabilities *cap) > +{ > + struct arm64_ftr_reg *aa32isar5 = get_arm64_ftr_reg(SYS_ID_ISAR5_EL1); > + u64 aes_mask = GENMASK_ULL(ID_ISAR5_AES_SHIFT + 3, ID_ISAR5_AES_SHIFT); > + > + /* > + * On affected platforms this call is made via stop_machine() on all > + * online CPUs. Only clear the register from the boot CPU. > + */ > + if (smp_processor_id()) > + return; > + > + aa32isar5->sys_val &= ~aes_mask; > +} > +#endif /* CONFIG_ARM64_ERRATUM_1742098 */ I wonder whether this would look better if we use the ARM64_FTR_REG_OVERRIDE approach with an id_isar5_override defined in cpu_errata.c and populated there. I haven't checked the order in which they would be called though. Alternatively, we could make the ftr_id_isar5 reg global and patch it directly in cpu_errata.c (arm64_ftr_reg_ctrel0 is another case where we made it global). Yet another option would be to add some function in cpufeature.[hc] to patch a feature directly and we'd call it from cpu_errata.c. My preference would be to keep the cpu_enable function for the workaround in cpu_errata.c. Is this the first case where we need to change the ELF HWCAPs due to an erratum? -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel