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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKL
Date: Mon, 7 Feb 2022 11:45:54 +0200	[thread overview]
Message-ID: <YgDqUgGT7ioRHoDb@intel.com> (raw)
In-Reply-To: <20220207073048.GC2471@intel.com>

On Mon, Feb 07, 2022 at 09:30:48AM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Feb 04, 2022 at 04:18:18PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On TGL/RKL the BIOS likes to use some kind of bogus DBUF layout
> > that doesn't match what the spec recommends. With a single active
> > pipe that is not going to be a problem, but with multiple pipes
> > active skl_commit_modeset_enables() goes into an infinite loop
> > since it can't figure out any order in which it can commit the
> > pipes without causing DBUF overlaps between the planes.
> > 
> > We'd need some kind of extra DBUF defrag stage in between to
> > make the transition possible. But that is clearly way too complex
> > a solution, so in the name of simplicity let's just sanitize the
> > DBUF state by simply turning off all planes when we detect a
> > pipe encroaching on its neighbours' DBUF slices. We only have
> > to disable the primary planes as all other planes should have
> > already been disabled (if they somehow were enabled) by
> > earlier sanitization steps.
> > 
> > And for good measure let's also sanitize in case the DBUF
> > allocations of the pipes already seem to overlap each other.
> > 
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4762
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Thanks. Sprinkled on some cc:stable and pushed.

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2022-02-07  9:45 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-04 14:18 [Intel-gfx] [PATCH 1/3] drm/i915: Allow !join_mbus cases for adlp+ dbuf configuration Ville Syrjala
2022-02-04 14:18 ` [Intel-gfx] [PATCH 2/3] drm/i915: Populate pipe dbuf slices more accurately during readout Ville Syrjala
2022-02-07  7:30   ` Lisovskiy, Stanislav
2022-02-04 14:18 ` [Intel-gfx] [PATCH 3/3] drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKL Ville Syrjala
2022-02-07  7:30   ` Lisovskiy, Stanislav
2022-02-07  9:45     ` Ville Syrjälä [this message]
2022-02-04 15:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Allow !join_mbus cases for adlp+ dbuf configuration Patchwork
2022-02-04 16:27 ` [Intel-gfx] ✗ Fi.CI.IGT: " Patchwork
2022-02-07  7:29 ` [Intel-gfx] [PATCH 1/3] " Lisovskiy, Stanislav

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