Re: [PATCH v3 7/7] arm64: dts: qcom: sa8155: Enable PCIe nodes

[Bjorn Andersson <bjorn.andersson@linaro.org>]

On Thu 03 Mar 00:09 CST 2022, Bhupesh Sharma wrote:

> Hi Dmitry,
> 
> On Thu, 3 Mar 2022 at 02:29, Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> >
> > On Wed, 2 Mar 2022 at 23:31, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote:
> > >
> > > SA8155p ADP board supports the PCIe0 controller in the RC
> > > mode (only). So add the support for the same.
> > >
> > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > Cc: Vinod Koul <vkoul@kernel.org>
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > > ---
> > >  arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 42 ++++++++++++++++++++++++
> > >  1 file changed, 42 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> > > index 8756c2b25c7e..3f6b3ee404f5 100644
> > > --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> > > +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> > > @@ -387,9 +387,51 @@ &usb_2_qmpphy {
> > >         vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
> > >  };
> > >
> > > +&pcie0 {
> > > +       status = "okay";
> > > +};
> > > +
> > > +&pcie0_phy {
> > > +       status = "okay";
> > > +       vdda-phy-supply = <&vreg_l18c_0p88>;
> > > +       vdda-pll-supply = <&vreg_l8c_1p2>;
> > > +};
> > > +
> > > +&pcie1_phy {
> > > +       vdda-phy-supply = <&vreg_l18c_0p88>;
> > > +       vdda-pll-supply = <&vreg_l8c_1p2>;
> > > +};
> > > +
> > >  &tlmm {
> > >         gpio-reserved-ranges = <0 4>;
> > >
> > > +       bt_en_default: bt_en_default {

'_' is not a valid character in the node name (it is in the label).

> > > +               mux {

Please flatten this, you can omit the mux and config subnodes and put
the properties directly in the state node.

> > > +                       pins = "gpio172";
> > > +                       function = "gpio";
> > > +               };
> > > +
> > > +               config {
> > > +                       pins = "gpio172";
> > > +                       drive-strength = <2>;
> > > +                       bias-pull-down;
> > > +               };
> > > +       };
> > > +
> > > +       wlan_en_default: wlan_en_default {
> > > +               mux {
> > > +                       pins = "gpio169";
> > > +                       function = "gpio";
> > > +               };
> > > +
> > > +               config {
> > > +                       pins = "gpio169";
> > > +                       drive-strength = <16>;
> > > +                       output-high;
> > > +                       bias-pull-up;
> > > +               };
> > > +       };
> > > +
> >
> > Not related to PCIe
> 
> Hmm.. I have no strong personal opinion on this, so let's see what
> Bjorn thinks about the same.
> My reasoning for keeping it here was to just capture that we have
> 'bt_en' and 'wlan_en' related tlmm details here, so that when you send
> out the reworked QCAxxxx mfd series (see [1]) later, I can easily plug
> it in for SA8155p ADP dts as well with the 'bt' and 'wlan' constructs.
> 

The BT_EN is unrelated to PCIe, and I'm not able to see where you select
the wlan_en_default state, so this would be dangling.

So the bt_en should come in a patch together with a bluetooth node and
the wlan_en_default should come with something that ensures that the
WiFi portion of the chip is powered and the gpio enabled.

Regards,
Bjorn

> [1]. https://lore.kernel.org/lkml/20210621223141.1638189-2-dmitry.baryshkov@linaro.org/T/
> 
> Regards.
> Bhupesh
> 
> > >         usb2phy_ac_en1_default: usb2phy_ac_en1_default {
> > >                 mux {
> > >                         pins = "gpio113";
> > > --
> > > 2.35.1
> > >
> >
> >
> > --
> > With best wishes
> > Dmitry