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[34.68.225.194]) by smtp.gmail.com with ESMTPSA id a3-20020a5ec303000000b006496b4dd21csm774433iok.5.2022.03.23.19.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Mar 2022 19:26:33 -0700 (PDT) Date: Thu, 24 Mar 2022 02:26:30 +0000 From: Oliver Upton To: Ricardo Koller Subject: Re: [PATCH v6 11/25] KVM: arm64: Add remaining ID registers to id_reg_desc_table Message-ID: References: <20220311044811.1980336-1-reijiw@google.com> <20220311044811.1980336-12-reijiw@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: kvm@vger.kernel.org, Marc Zyngier , Peter Shier , Will Deacon , Paolo Bonzini , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Wed, Mar 23, 2022 at 10:25:35PM +0000, Oliver Upton wrote: > On Wed, Mar 23, 2022 at 03:22:43PM -0700, Ricardo Koller wrote: > > On Wed, Mar 23, 2022 at 08:44:26PM +0000, Oliver Upton wrote: > > > On Wed, Mar 23, 2022 at 01:13:32PM -0700, Ricardo Koller wrote: > > > > On Wed, Mar 23, 2022 at 07:53:14PM +0000, Oliver Upton wrote: > > > > > Hi Reiji, > > > > > > > > > > On Thu, Mar 10, 2022 at 08:47:57PM -0800, Reiji Watanabe wrote: > > > > > > Add hidden or reserved ID registers, and remaining ID registers, > > > > > > which don't require special handling, to id_reg_desc_table. > > > > > > Add 'flags' field to id_reg_desc, which is used to indicates hiddden > > > > > > or reserved registers. Since now id_reg_desc_init() is called even > > > > > > for hidden/reserved registers, change it to not do anything for them. > > > > > > > > > > > > Signed-off-by: Reiji Watanabe > > > > > > > > > > I think there is a very important detail of the series that probably > > > > > should be highlighted. We are only allowing AArch64 feature registers to > > > > > be configurable, right? AArch32 feature registers remain visible with > > > > > their default values passed through to the guest. If you've already > > > > > stated this as a precondition elsewhere then my apologies for the noise. > > > > > > > > Aren't AArch64 ID regs architecturally mapped to their AArch32 > > > > counterparts? They should show the same values. I'm not sure if it's a > > > > problem (and if KVM is faithful to that rule), > > > > > > I believe it's a bit more subtle than that. The AArch32 feature registers > > > are architecturally mapped to certain encodings accessible from AArch64. > > > For example, ID_PFR0_EL1 is actually a 64 bit register where bits [31:0] > > > map to the ID_PFR0 AArch32 register. ID_PFR0_EL1 is only accessible from > > > AArch64 with the MRS instruction, and ID_PFR0 is only accessible from > > > AArch32 with the MRC instruction. KVM just so happens to handle both of > > > these reads from the same sys_reg_desc. Ughhhhh. We actually clear HCR_EL2.TID3 for AArch32 guests, so AArch32 EL1 reads straight from hardware. Considering the work we put in to make sure feature registers are consistent system-wide and the limitations on certain features, this is plain wrong. I have a series that addresses this but need to go find some 32 bit hardware to test with :) -- Thanks, Oliver _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E49AC433EF for ; Thu, 24 Mar 2022 02:28:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LNy6CW8LDmsoRzAYHibJNZxeufJiuEOeAg8Q5fqNDvY=; b=r6EsTa52D8bdZk e4VNuNKcBGmyFtfiuJr/Lt52/OyCDuNLKSsGTIwqRdVdFnKUlZ+7iRE59ZcmkufjtATncTffjIv8M f5jNdVq7TwFtpGL3CfYHlxsQAqJ0CL8fUR559jDGrcRq4iZs/TocUorAdvA5ku7cRvAgnDc9tqUTP eM312dK4xN2+hCYPEVWnp914DEUktYILgBpAgIsBEIinSaeNDuRHWp3iky1qEP6UGqXvJAF8i3sUx T76LZ7qIlurTP2PNLSqSyp1jxsXi2FmX2anOIxCTy9qxeiHi2n4cFsWfENppQNZl5yxfOSqS1Ihat jkIlol3EQw+Tcn+B896A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nXDBP-00FSdL-ED; Thu, 24 Mar 2022 02:26:39 +0000 Received: from mail-io1-xd36.google.com ([2607:f8b0:4864:20::d36]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nXDBM-00FScY-9Q for linux-arm-kernel@lists.infradead.org; Thu, 24 Mar 2022 02:26:37 +0000 Received: by mail-io1-xd36.google.com with SMTP id e22so3919210ioe.11 for ; Wed, 23 Mar 2022 19:26:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=890X9ZlW/q/ZeZqirs7HvcNCWN7aGL7evmsesPaQNmQ=; b=rxX998mFFfKKFwyAeeJOshWSPWoXTtcDGc2Rs99n2aE5JPs2wCNBni5DWMWGDK5FKx Q7lLIGEqmOvSWff8vXIyOD5ZNt/HCfvrjTYtRVygUmtaS7rEK4hsmBPgiNSjolAwPt9B bEcqIk7A9aVcGT6tLAygknW8s63iFNnBVF7O1b6flHzqX0rdAHmWJFaDpNyRrWbESTdW w7w3go6IUFDbYKQPt+ig5iHmLmSpZdvceZhiU0rhomRZs+M2kx+IhNEDhVI3yxhdh2hX HG8dyKnD5kbiK/15DzoJOKw6fGH74ySt5vJZPCnhT2FsMkINzT7lCURMaC2F4D6EI9AF vl5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=890X9ZlW/q/ZeZqirs7HvcNCWN7aGL7evmsesPaQNmQ=; b=5IAmDdtNFMhbkbHsKkO6+BNRAeRys1DqC6edF1yHD5ZRxcHirGS9q6uSG0PNOz2unn kdYNQCmGCoDHVMHDaY5bAR8wTro5I7dfhi8MAJqf0BGgb5xoDbDBcqZwIARKnMZ0I1Cf n4jQNqdGPUW9E6/86jNuX5MMPRhnA79ELKB/wMMfCP0YdDP6wSO4Zt8/iiVxXKnebJoK hkCq35t9ThnHK3hWyvkCrb8awnfj/G692pfQaf8C4Yvv33T4wl22WNHlx7YlFZCjYQ+3 9MuJMg6rDaKNKr+FMKbSjvQhEmrNa6zgs9dIb6TjIlZ1af5iVmIOcc+ror47guIfEWsN F7bw== X-Gm-Message-State: AOAM5311r1ciwSkn9bZHa8glKTrIWBtXjEAuri5lszn0yL9WDMDHzIfc N/0DX3XUMB3WwJN66WSl/uV+Kg== X-Google-Smtp-Source: ABdhPJwIwB7dsVZCMZPmvWaa1HkqW3/JHdv1qtXXns+LPlUOuyK0nCVpB3hi5nVUva0OPPnhM1Z1Sg== X-Received: by 2002:a05:6638:3043:b0:314:7ce2:4a6e with SMTP id u3-20020a056638304300b003147ce24a6emr1650582jak.258.1648088794648; Wed, 23 Mar 2022 19:26:34 -0700 (PDT) Received: from google.com (194.225.68.34.bc.googleusercontent.com. [34.68.225.194]) by smtp.gmail.com with ESMTPSA id a3-20020a5ec303000000b006496b4dd21csm774433iok.5.2022.03.23.19.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Mar 2022 19:26:33 -0700 (PDT) Date: Thu, 24 Mar 2022 02:26:30 +0000 From: Oliver Upton To: Ricardo Koller Cc: Reiji Watanabe , Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Jing Zhang , Raghavendra Rao Anata Subject: Re: [PATCH v6 11/25] KVM: arm64: Add remaining ID registers to id_reg_desc_table Message-ID: References: <20220311044811.1980336-1-reijiw@google.com> <20220311044811.1980336-12-reijiw@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220323_192636_361620_CCC0224D X-CRM114-Status: GOOD ( 27.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Mar 23, 2022 at 10:25:35PM +0000, Oliver Upton wrote: > On Wed, Mar 23, 2022 at 03:22:43PM -0700, Ricardo Koller wrote: > > On Wed, Mar 23, 2022 at 08:44:26PM +0000, Oliver Upton wrote: > > > On Wed, Mar 23, 2022 at 01:13:32PM -0700, Ricardo Koller wrote: > > > > On Wed, Mar 23, 2022 at 07:53:14PM +0000, Oliver Upton wrote: > > > > > Hi Reiji, > > > > > > > > > > On Thu, Mar 10, 2022 at 08:47:57PM -0800, Reiji Watanabe wrote: > > > > > > Add hidden or reserved ID registers, and remaining ID registers, > > > > > > which don't require special handling, to id_reg_desc_table. > > > > > > Add 'flags' field to id_reg_desc, which is used to indicates hiddden > > > > > > or reserved registers. Since now id_reg_desc_init() is called even > > > > > > for hidden/reserved registers, change it to not do anything for them. > > > > > > > > > > > > Signed-off-by: Reiji Watanabe > > > > > > > > > > I think there is a very important detail of the series that probably > > > > > should be highlighted. We are only allowing AArch64 feature registers to > > > > > be configurable, right? AArch32 feature registers remain visible with > > > > > their default values passed through to the guest. If you've already > > > > > stated this as a precondition elsewhere then my apologies for the noise. > > > > > > > > Aren't AArch64 ID regs architecturally mapped to their AArch32 > > > > counterparts? They should show the same values. I'm not sure if it's a > > > > problem (and if KVM is faithful to that rule), > > > > > > I believe it's a bit more subtle than that. The AArch32 feature registers > > > are architecturally mapped to certain encodings accessible from AArch64. > > > For example, ID_PFR0_EL1 is actually a 64 bit register where bits [31:0] > > > map to the ID_PFR0 AArch32 register. ID_PFR0_EL1 is only accessible from > > > AArch64 with the MRS instruction, and ID_PFR0 is only accessible from > > > AArch32 with the MRC instruction. KVM just so happens to handle both of > > > these reads from the same sys_reg_desc. Ughhhhh. We actually clear HCR_EL2.TID3 for AArch32 guests, so AArch32 EL1 reads straight from hardware. Considering the work we put in to make sure feature registers are consistent system-wide and the limitations on certain features, this is plain wrong. I have a series that addresses this but need to go find some 32 bit hardware to test with :) -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F40BC433EF for ; Thu, 24 Mar 2022 02:26:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244635AbiCXC2K (ORCPT ); Wed, 23 Mar 2022 22:28:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347772AbiCXC2G (ORCPT ); Wed, 23 Mar 2022 22:28:06 -0400 Received: from mail-io1-xd2e.google.com (mail-io1-xd2e.google.com [IPv6:2607:f8b0:4864:20::d2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6709939B1 for ; Wed, 23 Mar 2022 19:26:35 -0700 (PDT) Received: by mail-io1-xd2e.google.com with SMTP id k25so3930429iok.8 for ; Wed, 23 Mar 2022 19:26:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=890X9ZlW/q/ZeZqirs7HvcNCWN7aGL7evmsesPaQNmQ=; b=rxX998mFFfKKFwyAeeJOshWSPWoXTtcDGc2Rs99n2aE5JPs2wCNBni5DWMWGDK5FKx Q7lLIGEqmOvSWff8vXIyOD5ZNt/HCfvrjTYtRVygUmtaS7rEK4hsmBPgiNSjolAwPt9B bEcqIk7A9aVcGT6tLAygknW8s63iFNnBVF7O1b6flHzqX0rdAHmWJFaDpNyRrWbESTdW w7w3go6IUFDbYKQPt+ig5iHmLmSpZdvceZhiU0rhomRZs+M2kx+IhNEDhVI3yxhdh2hX HG8dyKnD5kbiK/15DzoJOKw6fGH74ySt5vJZPCnhT2FsMkINzT7lCURMaC2F4D6EI9AF vl5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=890X9ZlW/q/ZeZqirs7HvcNCWN7aGL7evmsesPaQNmQ=; b=NNEm7WX4jPonQPZZvYzP6C9TJFVMyW+gr/itnZBCIVhABXZaEvIB0DV78AtRF0lXw1 JduSuMhpCwQmBLiiA71aXWw66DQEZGv6AcVuqTT3yk2ot955ZjcLrIAqzMv3Ejil0nIt hbLuuD9DrFbsV2WqHyg+Q9QFtc97w3aUn973UirFtaoSKXKZdjV+fdvLyfEtbJ4n1z4r CIyAm9HlH0JYb9fVHT+Qkx/wDj9SrnJbgPakmU8RRhDyuHiM0KmdfgWHHB/+SCHr07G7 QXI3lWUjyvWq96VFYeuS/vgY0fIoxi9HWZ5pICzYnCS9injXhvdb5aYeVBs7v5zT/N6P BbZg== X-Gm-Message-State: AOAM530R+DgksHVsflyG/GzCfgTt4SJHtsn1t2xhM5/yibnv10EVZv5Z t7VuXolvAk7t1I/xADftuqEvLg== X-Google-Smtp-Source: ABdhPJwIwB7dsVZCMZPmvWaa1HkqW3/JHdv1qtXXns+LPlUOuyK0nCVpB3hi5nVUva0OPPnhM1Z1Sg== X-Received: by 2002:a05:6638:3043:b0:314:7ce2:4a6e with SMTP id u3-20020a056638304300b003147ce24a6emr1650582jak.258.1648088794648; Wed, 23 Mar 2022 19:26:34 -0700 (PDT) Received: from google.com (194.225.68.34.bc.googleusercontent.com. [34.68.225.194]) by smtp.gmail.com with ESMTPSA id a3-20020a5ec303000000b006496b4dd21csm774433iok.5.2022.03.23.19.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Mar 2022 19:26:33 -0700 (PDT) Date: Thu, 24 Mar 2022 02:26:30 +0000 From: Oliver Upton To: Ricardo Koller Cc: Reiji Watanabe , Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Jing Zhang , Raghavendra Rao Anata Subject: Re: [PATCH v6 11/25] KVM: arm64: Add remaining ID registers to id_reg_desc_table Message-ID: References: <20220311044811.1980336-1-reijiw@google.com> <20220311044811.1980336-12-reijiw@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, Mar 23, 2022 at 10:25:35PM +0000, Oliver Upton wrote: > On Wed, Mar 23, 2022 at 03:22:43PM -0700, Ricardo Koller wrote: > > On Wed, Mar 23, 2022 at 08:44:26PM +0000, Oliver Upton wrote: > > > On Wed, Mar 23, 2022 at 01:13:32PM -0700, Ricardo Koller wrote: > > > > On Wed, Mar 23, 2022 at 07:53:14PM +0000, Oliver Upton wrote: > > > > > Hi Reiji, > > > > > > > > > > On Thu, Mar 10, 2022 at 08:47:57PM -0800, Reiji Watanabe wrote: > > > > > > Add hidden or reserved ID registers, and remaining ID registers, > > > > > > which don't require special handling, to id_reg_desc_table. > > > > > > Add 'flags' field to id_reg_desc, which is used to indicates hiddden > > > > > > or reserved registers. Since now id_reg_desc_init() is called even > > > > > > for hidden/reserved registers, change it to not do anything for them. > > > > > > > > > > > > Signed-off-by: Reiji Watanabe > > > > > > > > > > I think there is a very important detail of the series that probably > > > > > should be highlighted. We are only allowing AArch64 feature registers to > > > > > be configurable, right? AArch32 feature registers remain visible with > > > > > their default values passed through to the guest. If you've already > > > > > stated this as a precondition elsewhere then my apologies for the noise. > > > > > > > > Aren't AArch64 ID regs architecturally mapped to their AArch32 > > > > counterparts? They should show the same values. I'm not sure if it's a > > > > problem (and if KVM is faithful to that rule), > > > > > > I believe it's a bit more subtle than that. The AArch32 feature registers > > > are architecturally mapped to certain encodings accessible from AArch64. > > > For example, ID_PFR0_EL1 is actually a 64 bit register where bits [31:0] > > > map to the ID_PFR0 AArch32 register. ID_PFR0_EL1 is only accessible from > > > AArch64 with the MRS instruction, and ID_PFR0 is only accessible from > > > AArch32 with the MRC instruction. KVM just so happens to handle both of > > > these reads from the same sys_reg_desc. Ughhhhh. We actually clear HCR_EL2.TID3 for AArch32 guests, so AArch32 EL1 reads straight from hardware. Considering the work we put in to make sure feature registers are consistent system-wide and the limitations on certain features, this is plain wrong. I have a series that addresses this but need to go find some 32 bit hardware to test with :) -- Thanks, Oliver