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[34.68.225.194]) by smtp.gmail.com with ESMTPSA id m9-20020a0566022ac900b0064cf3d9f35fsm8889296iov.35.2022.04.07.13.13.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 13:13:25 -0700 (PDT) Date: Thu, 7 Apr 2022 20:13:22 +0000 From: Oliver Upton To: Marc Zyngier Subject: Re: [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES} Message-ID: References: <20220405182327.205520-1-maz@kernel.org> <20220405182327.205520-2-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220405182327.205520-2-maz@kernel.org> Cc: Lorenzo Pieralisi , kvm@vger.kernel.org, Andre Przywara , kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Tue, Apr 05, 2022 at 07:23:24PM +0100, Marc Zyngier wrote: > As we're about to expose GICR_CTLR.{IR,CES} to guests, populate > the include file with the architectural values. > > Signed-off-by: Marc Zyngier Reviewed-by: Oliver Upton > --- > include/linux/irqchip/arm-gic-v3.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h > index 12d91f0dedf9..728691365464 100644 > --- a/include/linux/irqchip/arm-gic-v3.h > +++ b/include/linux/irqchip/arm-gic-v3.h > @@ -127,6 +127,8 @@ > #define GICR_PIDR2 GICD_PIDR2 > > #define GICR_CTLR_ENABLE_LPIS (1UL << 0) > +#define GICR_CTLR_CES (1UL << 1) > +#define GICR_CTLR_IR (1UL << 2) > #define GICR_CTLR_RWP (1UL << 3) > > #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) > -- > 2.34.1 > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB83EC433EF for ; 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[34.68.225.194]) by smtp.gmail.com with ESMTPSA id m9-20020a0566022ac900b0064cf3d9f35fsm8889296iov.35.2022.04.07.13.13.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 13:13:25 -0700 (PDT) Date: Thu, 7 Apr 2022 20:13:22 +0000 From: Oliver Upton To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, James Morse , Suzuki K Poulose , Alexandru Elisei , Andre Przywara , Eric Auger , Lorenzo Pieralisi , kernel-team@android.com Subject: Re: [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES} Message-ID: References: <20220405182327.205520-1-maz@kernel.org> <20220405182327.205520-2-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220405182327.205520-2-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220407_131329_745772_6201C06F X-CRM114-Status: GOOD ( 15.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 05, 2022 at 07:23:24PM +0100, Marc Zyngier wrote: > As we're about to expose GICR_CTLR.{IR,CES} to guests, populate > the include file with the architectural values. > > Signed-off-by: Marc Zyngier Reviewed-by: Oliver Upton > --- > include/linux/irqchip/arm-gic-v3.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h > index 12d91f0dedf9..728691365464 100644 > --- a/include/linux/irqchip/arm-gic-v3.h > +++ b/include/linux/irqchip/arm-gic-v3.h > @@ -127,6 +127,8 @@ > #define GICR_PIDR2 GICD_PIDR2 > > #define GICR_CTLR_ENABLE_LPIS (1UL << 0) > +#define GICR_CTLR_CES (1UL << 1) > +#define GICR_CTLR_IR (1UL << 2) > #define GICR_CTLR_RWP (1UL << 3) > > #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31FC4C433F5 for ; Thu, 7 Apr 2022 20:15:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229463AbiDGURo (ORCPT ); Thu, 7 Apr 2022 16:17:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229495AbiDGURl (ORCPT ); Thu, 7 Apr 2022 16:17:41 -0400 Received: from mail-io1-xd29.google.com (mail-io1-xd29.google.com [IPv6:2607:f8b0:4864:20::d29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D71E94882D0 for ; Thu, 7 Apr 2022 13:14:11 -0700 (PDT) Received: by mail-io1-xd29.google.com with SMTP id p135so2314170iod.2 for ; Thu, 07 Apr 2022 13:14:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=kPv+ZIqzYvRek0cRdeMz/lWApF7cflqzGAwQSPk+D1g=; b=Vwbqolr+6WT9PZrvXSXV5eov3RfxCF9Upd51VWIyqZ1pqFcKZHmhRT9XnGsCkAHh05 77l+zhWDpahLE5pUMG2B9j/nHIow4aw7XhZE+CsSD6z70hacoC3z1u+YNAcvKOfmrl3z fozVlMJs5iyRJSBg08fuwghJvWzY560AYZL5ZuaFcEn1PyVflPyG6JqaZHWqg2VH9Dfm OsUOi04iKG8rhuloDFnUSFpDocTzzSV6TJdRNMR01P/OfGl0U+E/ZBMTWX3uW0CSCFhQ si22K91rT3Z2Gb69hvZGq6tifarLk26cRL26z+WGWPuJmDLabL4zz9Fz0utJth5ajpZ/ o2nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=kPv+ZIqzYvRek0cRdeMz/lWApF7cflqzGAwQSPk+D1g=; b=4CBfVz3wDi2O2ROEbzDLheBaptlN3qK0KpPbQkmpGHV4QALH5tx6ODPWqw5W0+G/11 iy3d0qkntSm+gMPhDT8Prd7LtsfsnE5UeKiuDhB0AbrGyA1LMVqFJ8CQR//p8n94wu2M Cx9seMIb3FmeEUjA7nPK4yTJ2iohV5lxcm3brBOZCPUftoAu42AA3TO3nljX7FTD1QyT jpnPy5fUb3YmahdBmZ4LOKMM7yi0wJSGNtsTZ8JpCKn1FEqsYA6m+ruC28jzYw9Z8Cku sRVYypA2m3WeYtopVdJYd07GGKGlf/BcA4wo9b+3/toPeeMQTQZSarzbcuCTiMkz3OLs mRKg== X-Gm-Message-State: AOAM530Tt8zz1mcRWxKB5sXcASuB/GfB7wZd08V+9XAMaSJCfunrJj4h TvL9XS6l2h0GFWYMztB8FnKbIg== X-Google-Smtp-Source: ABdhPJx5V2vUqUS2eTOHLtK7IH0eyx7bh5pFcMTMmAj8gSnHQ2ix1EFqPmZe47max8+jfJKS65ClQQ== X-Received: by 2002:a05:6638:d47:b0:321:460a:88c8 with SMTP id d7-20020a0566380d4700b00321460a88c8mr7430290jak.175.1649362406410; Thu, 07 Apr 2022 13:13:26 -0700 (PDT) Received: from google.com (194.225.68.34.bc.googleusercontent.com. [34.68.225.194]) by smtp.gmail.com with ESMTPSA id m9-20020a0566022ac900b0064cf3d9f35fsm8889296iov.35.2022.04.07.13.13.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 13:13:25 -0700 (PDT) Date: Thu, 7 Apr 2022 20:13:22 +0000 From: Oliver Upton To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, James Morse , Suzuki K Poulose , Alexandru Elisei , Andre Przywara , Eric Auger , Lorenzo Pieralisi , kernel-team@android.com Subject: Re: [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES} Message-ID: References: <20220405182327.205520-1-maz@kernel.org> <20220405182327.205520-2-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220405182327.205520-2-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Tue, Apr 05, 2022 at 07:23:24PM +0100, Marc Zyngier wrote: > As we're about to expose GICR_CTLR.{IR,CES} to guests, populate > the include file with the architectural values. > > Signed-off-by: Marc Zyngier Reviewed-by: Oliver Upton > --- > include/linux/irqchip/arm-gic-v3.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h > index 12d91f0dedf9..728691365464 100644 > --- a/include/linux/irqchip/arm-gic-v3.h > +++ b/include/linux/irqchip/arm-gic-v3.h > @@ -127,6 +127,8 @@ > #define GICR_PIDR2 GICD_PIDR2 > > #define GICR_CTLR_ENABLE_LPIS (1UL << 0) > +#define GICR_CTLR_CES (1UL << 1) > +#define GICR_CTLR_IR (1UL << 2) > #define GICR_CTLR_RWP (1UL << 3) > > #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) > -- > 2.34.1 >