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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Naveen Krishna Chatradhi <nchatrad@amd.com>
Cc: linux-edac@vger.kernel.org, bp@alien8.de, mingo@redhat.com,
	mchehab@kernel.org, Muralidhara M K <muralimk@amd.com>
Subject: Re: [PATCH 12/14] EDAC/amd64: Add dump_misc_regs() into pvt->ops
Date: Mon, 28 Mar 2022 16:58:18 +0000	[thread overview]
Message-ID: <YkHpKgPC9BO7NuA+@yaz-ubuntu> (raw)
In-Reply-To: <20220228161354.54923-13-nchatrad@amd.com>

On Mon, Feb 28, 2022 at 09:43:52PM +0530, Naveen Krishna Chatradhi wrote:
> From: Muralidhara M K <muralimk@amd.com>
> 
> Add function pointer for dump_misc_regs() in pvt->ops and assign
> family specific dump_misc_regs() definitions appropriately.

Please include the "why".

> 
> Signed-off-by: Muralidhara M K <muralimk@amd.com>
> Signed-off-by: Naveen Krishna Chatradhi <nchatrad@amd.com>
> ---
> This patch is created by splitting the 5/12th patch in series
> [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/
> 
>  drivers/edac/amd64_edac.c | 25 ++++++++++++++-----------
>  drivers/edac/amd64_edac.h |  1 +
>  2 files changed, 15 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index a799594c9574..1063dda20ce9 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -1442,6 +1442,10 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt)
>  
>  	edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",
>  		 pvt->dhar, dhar_base(pvt));
> +
> +	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
> +

This line can be dropped when dhar is removed for current systems.

> +	amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);

This line can be dropped if we decide that symbol size isn't needed on current
systems. We should double check if it's needed when determining "edac_mode".

If we keep it, then it should be printed at the end of the function where we
read the symbol size.

>  }
>  
>  /* Display and decode various NB registers for debug purposes. */
> @@ -1476,15 +1480,6 @@ static void __dump_misc_regs(struct amd64_pvt *pvt)
>  	/* Only if NOT ganged does dclr1 have valid info */
>  	if (!dct_ganging_enabled(pvt))
>  		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
> -}
> -
> -/* Display and decode various NB registers for debug purposes. */
> -static void dump_misc_regs(struct amd64_pvt *pvt)
> -{
> -	if (pvt->umc)
> -		__dump_misc_regs_df(pvt);
> -	else
> -		__dump_misc_regs(pvt);
>  
>  	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
>  
> @@ -3803,6 +3798,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs;
>  		break;
>  
>  	case 0x10:
> @@ -3822,6 +3818,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs;
>  		break;
>  
>  	case 0x15:
> @@ -3857,6 +3854,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs;
>  		break;
>  
>  	case 0x16:
> @@ -3882,6 +3880,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs;
>  		break;
>  
>  	case 0x17:
> @@ -3921,6 +3920,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f17_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows_df;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs_df;
>  
>  		if (pvt->fam == 0x18) {
>  			pvt->ctl_name			= "F18h";
> @@ -3966,6 +3966,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f17_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows_df;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs_df;

I think the underscore prefixes can be dropped.

>  		break;
>  
>  	default:
> @@ -3979,7 +3980,8 @@ static int per_family_init(struct amd64_pvt *pvt)
>  	    !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz ||
>  	    !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled ||
>  	    !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap ||
> -	    !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows) {
> +	    !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows ||
> +	    !pvt->ops->dump_misc_regs) {
>  		edac_dbg(1, "Common helper routines not defined.\n");
>  		return -EFAULT;
>  	}
> @@ -4169,7 +4171,8 @@ static int probe_one_instance(unsigned int nid)
>  
>  	amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id);
>  
> -	dump_misc_regs(pvt);
> +	/* Display and decode various NB registers for debug purposes. */

Please drop "NB" from the comment since other registers can also be printed.

Thanks,
Yazen

  reply	other threads:[~2022-03-28 16:58 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-28 16:13 [PATCH 00/14] EDAC/amd64: move platform specific routines to pvt->ops Naveen Krishna Chatradhi
2022-02-28 16:13 ` [PATCH 01/14] EDAC/amd64: Move struct fam_type variables into struct amd64_pvt Naveen Krishna Chatradhi
2022-03-23 17:19   ` Yazen Ghannam
2022-03-23 21:25     ` Borislav Petkov
     [not found]     ` <37449efc-1157-1d48-ec2e-726bf6c7edcb@amd.com>
2022-04-04 18:00       ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 02/14] EDAC/amd64: Add get_base_mask() into pvt->ops Naveen Krishna Chatradhi
2022-03-23 17:33   ` Yazen Ghannam
2022-03-23 17:34     ` Borislav Petkov
2022-02-28 16:13 ` [PATCH 03/14] EDAC/amd64: Add prep_chip_selects() " Naveen Krishna Chatradhi
2022-03-23 18:16   ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 04/14] EDAC/amd64: Add determine_memory_type() " Naveen Krishna Chatradhi
2022-03-23 18:20   ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 05/14] EDAC/amd64: Add get_ecc_sym_sz() " Naveen Krishna Chatradhi
2022-03-23 18:30   ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 06/14] EDAC/amd64: Add get_mc_regs() " Naveen Krishna Chatradhi
2022-03-28 16:08   ` Yazen Ghannam
2022-03-31 12:19     ` Chatradhi, Naveen Krishna
2022-04-04 18:19       ` Yazen Ghannam
2022-04-04 18:27         ` Borislav Petkov
2022-02-28 16:13 ` [PATCH 07/14] EDAC/amd64: Add ecc_enabled() " Naveen Krishna Chatradhi
2022-03-28 16:17   ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 08/14] EDAC/amd64: Add determine_edac_cap() " Naveen Krishna Chatradhi
2022-03-28 16:22   ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 09/14] EDAC/amd64: Add determine_edac_ctl_cap() " Naveen Krishna Chatradhi
2022-03-28 16:26   ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 10/14] EDAC/amd64: Add setup_mci_misc_sttrs() " Naveen Krishna Chatradhi
2022-03-28 16:39   ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 11/14] EDAC/amd64: Add populate_csrows() " Naveen Krishna Chatradhi
2022-03-28 16:47   ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 12/14] EDAC/amd64: Add dump_misc_regs() " Naveen Krishna Chatradhi
2022-03-28 16:58   ` Yazen Ghannam [this message]
2022-02-28 16:13 ` [PATCH 13/14] EDAC/amd64: Add get_cs_mode() " Naveen Krishna Chatradhi
2022-03-28 17:00   ` Yazen Ghannam
2022-02-28 16:13 ` [PATCH 14/14] EDAC/amd64: Add get_umc_error_info() " Naveen Krishna Chatradhi
2022-03-28 17:13   ` Yazen Ghannam

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