From: Rob Herring <robh@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: netdev@vger.kernel.org, pabeni@redhat.com,
robert.hancock@calian.com, davem@davemloft.net,
robh+dt@kernel.org, devicetree@vger.kernel.org,
linux@armlinux.org.uk, kuba@kernel.org, michal.simek@xilinx.com,
radhey.shyam.pandey@xilinx.com,
Greentime Hu <greentime.hu@sifive.com>,
andrew@lunn.ch
Subject: Re: [PATCH v7 net 3/4] dt-bindings: net: add pcs-handle attribute
Date: Mon, 4 Apr 2022 13:08:46 -0500 [thread overview]
Message-ID: <Yks0LoizNfx2uVmu@robh.at.kernel.org> (raw)
In-Reply-To: <20220329024921.2739338-4-andy.chiu@sifive.com>
On Tue, 29 Mar 2022 10:49:20 +0800, Andy Chiu wrote:
> Document the new pcs-handle attribute to support connecting to an
> external PHY. For Xilinx's AXI Ethernet, this is used when the core
> operates in SGMII or 1000Base-X modes and links through the internal
> PCS/PMA PHY.
>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
> ---
> .../devicetree/bindings/net/ethernet-controller.yaml | 6 ++++++
> Documentation/devicetree/bindings/net/xilinx_axienet.txt | 8 +++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2022-04-04 21:17 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-29 2:49 [PATCH v7 net 0/4] Fix broken link on Xilinx's AXI Ethernet in SGMII mode Andy Chiu
2022-03-29 2:49 ` [PATCH v7 net 1/4] net: axienet: setup mdio unconditionally Andy Chiu
2022-03-29 2:49 ` [PATCH v7 net 2/4] net: axienet: factor out phy_node in struct axienet_local Andy Chiu
2022-03-29 2:49 ` [PATCH v7 net 3/4] dt-bindings: net: add pcs-handle attribute Andy Chiu
2022-04-04 18:08 ` Rob Herring [this message]
2022-03-29 2:49 ` [PATCH v7 net 4/4] net: axiemac: use a phandle to reference pcs_phy Andy Chiu
2022-03-29 22:56 ` Jakub Kicinski
2022-03-30 1:25 ` Andrew Lunn
2022-03-30 1:48 ` Jakub Kicinski
2022-03-30 8:50 ` Andy Chiu
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