Re: [PATCH v7 5/8] KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode

[Sean Christopherson <seanjc@google.com>]

On Sat, Apr 02, 2022, Zeng Guang wrote:
> 
> > > -	/* TODO: optimize to just emulate side effect w/o one more write */
> > > -	kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
> > > +		kvm_lapic_msr_read(apic, offset, &val);
> > > +		kvm_apic_send_ipi(apic, (u32)val, (u32)(val >> 32));
> > This needs to clear the APIC_ICR_BUSY bit.  It'd also be nice to trace this write.
> > The easiest thing is to use kvm_x2apic_icr_write().  Kinda silly as it'll generate
> > an extra write, but on the plus side the TODO comment doesn't have to move :-D
> > 
> > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> > index c4c3155d98db..58bf296ee313 100644
> > --- a/arch/x86/kvm/lapic.c
> > +++ b/arch/x86/kvm/lapic.c
> > @@ -2230,6 +2230,7 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
> >          struct kvm_lapic *apic = vcpu->arch.apic;
> >          u64 val;
> > 
> > +       /* TODO: optimize to just emulate side effect w/o one more write */
> >          if (apic_x2apic_mode(apic)) {
> >                  /*
> >                   * When guest APIC is in x2APIC mode and IPI virtualization
> > @@ -2240,10 +2241,9 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
> >                          return;
> > 
> >                  kvm_lapic_msr_read(apic, offset, &val);
> > -               kvm_apic_send_ipi(apic, (u32)val, (u32)(val >> 32));
> > +               kvm_x2apic_icr_write(apic, val);
> 
> As SDM section 10.12.9 "ICR Operation in X2APIC mode" says "Delivery status
> bit is removed since it is not needed in x2APIC mode" , so that's not
> necessary to clear the APIC_ICR_BUSY bit here. Alternatively we can add trace
> to this write by hardware.

That same section later says 

  With the removal of the Delivery Status bit, system software no longer has a
  reason to read the ICR. It remains readable only to aid in debugging; however,
  software should not assume the value returned by reading the ICR is the last
  written value.

which means that it's at least legal for a hypervisor to clear the busy bit.  That
might be useful for debugging IPI issues?  Probably a bit of a stretch, e.g. I doubt
any kernels set the busy bit.  But, I do think the tracing would be helpful, and at
that point, the extra code should be an AND+MOV.

I don't have a super strong opinion, and I'm being somewhat hypocritical (see commit
b51818afdc1d ("KVM: SVM: Don't rewrite guest ICR on AVIC IPI virtualization failure"),
though that has dedicated tracing), so either approach works for me.