From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC273C433F5 for ; Wed, 20 Apr 2022 21:31:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YQ2Ys1cuZFPdnA8bE50qvQCahTXPper5SmEm9a+XCAc=; b=oa7oXNZr1GYvgY AAR8ufd+zAi8qx1hGWidsaX4W4U2tQ0bJmVz1T9iOGYoP1ZdoTyemi1s6YPHRDOpxqSzT++npUqKs 7Vylri2nbPPsi0n8umSi8KVAi2bufHJHJMoU0EUTAdUpr0SPfXEuNNHBkLGy0NTcJQvCusBQKqyJF Bd2si3arg7XxUAwsoGZwteaxrqwz/k4p3DLywmrqoCykKXYUSkQqe4qnw5+vfHrpIcfpPJXWNgslF +BK0HdbKRee8ZTpVfPEphNbhgJqNTsnOuWrtkh4xibLQdndjsEAPGlPPNLxpkNJaprId18e64HZ7M ho1X8RCcDCukBj608LMQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhHuE-00ARy8-1M; Wed, 20 Apr 2022 21:30:34 +0000 Received: from mail-oi1-f172.google.com ([209.85.167.172]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhHuA-00ARxC-2n for linux-arm-kernel@lists.infradead.org; Wed, 20 Apr 2022 21:30:31 +0000 Received: by mail-oi1-f172.google.com with SMTP id r85so3547097oie.7 for ; Wed, 20 Apr 2022 14:30:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=oKAyPnurUXqIpBjCXwQJqvX5yNXzu0aL/OrfPo6b7fE=; b=rqsno4vtXYS6N2oq1h0bUHtD9JhotUXlgJz3I1OyfoIxYblZpKp67ftTDkIMIXzkYj +crRCK5FBcoUoIKcFCPX98DVhGScvYWmpF7ZsITmi2YKlskH23YfPqQMoosSKolobNnb 1uPdSHdctq/x12QhLpzbBOlINs4eBi7wWSrgl6Nymn+RI1X8LS8AFEUY5VjIQnbNkYYr OahsBeMJRSDThGyADbljxGVmnbpd1nYtcRkQu+6qEBwgPZB8omp5Ki0hs64MuWdrtSez bkgCAJ09yIwr02vPj+l0zEPzphGwYcYcf7+GUulT3Z/DGheHPbznGvsYldztZLFz4zyx 3eDQ== X-Gm-Message-State: AOAM532fmpwsOUYyUoXYPW8v8BGioDWFc0okt0/iUHm/nTesqAR/eNhX hjVhtIT5k9qBWq8Y8rN5Fg== X-Google-Smtp-Source: ABdhPJxq9dTo9U+3/KCPdMhKSiga9fBO1UGN4lQPRboNsT8JQZfOkPOQL2vKXUutOjDSBWzmgyVeRA== X-Received: by 2002:a05:6808:1691:b0:2f9:4bd7:581e with SMTP id bb17-20020a056808169100b002f94bd7581emr2558521oib.144.1650490225602; Wed, 20 Apr 2022 14:30:25 -0700 (PDT) Received: from robh.at.kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id pp23-20020a0568709d1700b000e2d876505dsm406800oab.32.2022.04.20.14.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 14:30:25 -0700 (PDT) Received: (nullmailer pid 1882568 invoked by uid 1000); Wed, 20 Apr 2022 21:30:24 -0000 Date: Wed, 20 Apr 2022 16:30:24 -0500 From: Rob Herring To: Tomi Valkeinen Cc: Jyri Sarha , Vignesh Raghavendra , Nishanth Menon , DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia Subject: Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Message-ID: References: <20220419070302.16502-1-a-bhatia1@ti.com> <20220419070302.16502-2-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220420_143030_164272_02A32D7C X-CRM114-Status: GOOD ( 20.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 20, 2022 at 10:05:34AM +0300, Tomi Valkeinen wrote: > Hi, > > On 19/04/2022 17:20, Rob Herring wrote: > > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote: > > > The DSS IP on the ti-am65x soc supports an additional register space, > > > named "common1". Further. the IP services a maximum number of 2 > > > interrupts. > > > > > > Add the missing register space "common1" and the additional interrupt. > > > > > > Signed-off-by: Aradhya Bhatia > > > --- > > > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- > > > 1 file changed, 7 insertions(+), 3 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > index 5c7d2cbc4aac..102059e9e0d5 100644 > > > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > @@ -26,6 +26,7 @@ properties: > > > Addresses to each DSS memory region described in the SoC's TRM. > > > items: > > > - description: common DSS register area > > > + - description: common1 DSS register area > > > > You've just broken the ABI. > > > > New entries have to go on the end. > > I'm curious, if the 'reg-names' is a required property, as it is here, does > this still break the ABI? Yes, the order is part of the ABI. Sometimes we just give up with multiple optional entries or inherited any order allowed, but here there is no reason. Just add 'common1' to the end. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 794FCC433EF for ; Wed, 20 Apr 2022 21:30:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382524AbiDTVdR (ORCPT ); Wed, 20 Apr 2022 17:33:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382508AbiDTVdP (ORCPT ); Wed, 20 Apr 2022 17:33:15 -0400 Received: from mail-oi1-f176.google.com (mail-oi1-f176.google.com [209.85.167.176]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B198D2655A; Wed, 20 Apr 2022 14:30:27 -0700 (PDT) Received: by mail-oi1-f176.google.com with SMTP id e189so3530734oia.8; Wed, 20 Apr 2022 14:30:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=oKAyPnurUXqIpBjCXwQJqvX5yNXzu0aL/OrfPo6b7fE=; b=72ej5YFKxoOpmIPvWoaG4UMsWSl06JuRkoEU2spjYIqa/yRzTdV3NVWIg1e24CBQb4 Zvq2oMl3eY7r6PWKqz30kXiuDa9rc1TqSJ1yWVpj+DZiSHUY+SpRs30nMg8DWZfd66jO PCOTDfqrx2f0H9Vl22c44vmTRyvdboU+ifvWEpw3q9hi533nVp97EYfmxmk+h3/ECF5Q DfAqclOBW4ENdFDuZ9A7aJpfOE431mFQOF75CKRryPReo+wSzoAgYDJ2SlYSB9X7s/Pi vUOw2UHYMJJnEwTOqZ72ZK8N0KdGHXAc75sTDTffZc07tyFth7HKY81vNNqp6Dgt07KZ mMzQ== X-Gm-Message-State: AOAM530GAJ4vPpWxKy01F0TnEKBGqCy5t2Mckt5zbzaH4tilwq0Ij0SV 38tG1nAPPEkQZD/1/kOGml2nAUvuIw== X-Google-Smtp-Source: ABdhPJxq9dTo9U+3/KCPdMhKSiga9fBO1UGN4lQPRboNsT8JQZfOkPOQL2vKXUutOjDSBWzmgyVeRA== X-Received: by 2002:a05:6808:1691:b0:2f9:4bd7:581e with SMTP id bb17-20020a056808169100b002f94bd7581emr2558521oib.144.1650490225602; Wed, 20 Apr 2022 14:30:25 -0700 (PDT) Received: from robh.at.kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id pp23-20020a0568709d1700b000e2d876505dsm406800oab.32.2022.04.20.14.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 14:30:25 -0700 (PDT) Received: (nullmailer pid 1882568 invoked by uid 1000); Wed, 20 Apr 2022 21:30:24 -0000 Date: Wed, 20 Apr 2022 16:30:24 -0500 From: Rob Herring To: Tomi Valkeinen Cc: Jyri Sarha , Vignesh Raghavendra , Nishanth Menon , DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia Subject: Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Message-ID: References: <20220419070302.16502-1-a-bhatia1@ti.com> <20220419070302.16502-2-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Apr 20, 2022 at 10:05:34AM +0300, Tomi Valkeinen wrote: > Hi, > > On 19/04/2022 17:20, Rob Herring wrote: > > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote: > > > The DSS IP on the ti-am65x soc supports an additional register space, > > > named "common1". Further. the IP services a maximum number of 2 > > > interrupts. > > > > > > Add the missing register space "common1" and the additional interrupt. > > > > > > Signed-off-by: Aradhya Bhatia > > > --- > > > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- > > > 1 file changed, 7 insertions(+), 3 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > index 5c7d2cbc4aac..102059e9e0d5 100644 > > > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > @@ -26,6 +26,7 @@ properties: > > > Addresses to each DSS memory region described in the SoC's TRM. > > > items: > > > - description: common DSS register area > > > + - description: common1 DSS register area > > > > You've just broken the ABI. > > > > New entries have to go on the end. > > I'm curious, if the 'reg-names' is a required property, as it is here, does > this still break the ABI? Yes, the order is part of the ABI. Sometimes we just give up with multiple optional entries or inherited any order allowed, but here there is no reason. Just add 'common1' to the end. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0416BC433F5 for ; Wed, 20 Apr 2022 21:30:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FA1710F2C0; Wed, 20 Apr 2022 21:30:29 +0000 (UTC) Received: from mail-oi1-f180.google.com (mail-oi1-f180.google.com [209.85.167.180]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD3CD10F2C0 for ; Wed, 20 Apr 2022 21:30:27 +0000 (UTC) Received: by mail-oi1-f180.google.com with SMTP id a10so3536346oif.9 for ; Wed, 20 Apr 2022 14:30:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=oKAyPnurUXqIpBjCXwQJqvX5yNXzu0aL/OrfPo6b7fE=; b=QTizAuTVVj26nzyuZTvyXFwdX/gBWHv3qEb6hNWSI1LqTh+q9u4skuvBWc2u2M5iaM fV9zlN4AnBWrRSva1WdPUTZXNUWCwszSjU/EKLTp8714L/UiaeTsrk5NUbRkBlRv2lWV wqPWfy6FeHrswI0BvLmKE0Yf+0Ou4e10smifXqqGmAjG7JA4NHuHdI5xEPSga9vPg1oX gp3LWWbyA0JYDowDKXAAUvDbnJRPOdxZ9QLmBtM3DEzswmfdPnv768GY+2WdmBAsF7rE xMZKYleKd6Xbg6ZUQXnWqgztwfi/OM6WSnZpkbZbUt+Xg/nu4MFD3fs3RHQdPvJ/rSzh bdgw== X-Gm-Message-State: AOAM532+2XAWOfN44yNdWVseU1nlxCX+ESXmLkzxqaVoFiz8BZ7T7lgV 0gb7+GZ0wCFpMhOlqKJOvA== X-Google-Smtp-Source: ABdhPJxq9dTo9U+3/KCPdMhKSiga9fBO1UGN4lQPRboNsT8JQZfOkPOQL2vKXUutOjDSBWzmgyVeRA== X-Received: by 2002:a05:6808:1691:b0:2f9:4bd7:581e with SMTP id bb17-20020a056808169100b002f94bd7581emr2558521oib.144.1650490225602; Wed, 20 Apr 2022 14:30:25 -0700 (PDT) Received: from robh.at.kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id pp23-20020a0568709d1700b000e2d876505dsm406800oab.32.2022.04.20.14.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 14:30:25 -0700 (PDT) Received: (nullmailer pid 1882568 invoked by uid 1000); Wed, 20 Apr 2022 21:30:24 -0000 Date: Wed, 20 Apr 2022 16:30:24 -0500 From: Rob Herring To: Tomi Valkeinen Subject: Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Message-ID: References: <20220419070302.16502-1-a-bhatia1@ti.com> <20220419070302.16502-2-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree , Vignesh Raghavendra , Aradhya Bhatia , Linux Kernel , DRI Development , Jyri Sarha , Nikhil Devshatwar , Linux ARM Kernel Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Apr 20, 2022 at 10:05:34AM +0300, Tomi Valkeinen wrote: > Hi, > > On 19/04/2022 17:20, Rob Herring wrote: > > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote: > > > The DSS IP on the ti-am65x soc supports an additional register space, > > > named "common1". Further. the IP services a maximum number of 2 > > > interrupts. > > > > > > Add the missing register space "common1" and the additional interrupt. > > > > > > Signed-off-by: Aradhya Bhatia > > > --- > > > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- > > > 1 file changed, 7 insertions(+), 3 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > index 5c7d2cbc4aac..102059e9e0d5 100644 > > > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > @@ -26,6 +26,7 @@ properties: > > > Addresses to each DSS memory region described in the SoC's TRM. > > > items: > > > - description: common DSS register area > > > + - description: common1 DSS register area > > > > You've just broken the ABI. > > > > New entries have to go on the end. > > I'm curious, if the 'reg-names' is a required property, as it is here, does > this still break the ABI? Yes, the order is part of the ABI. Sometimes we just give up with multiple optional entries or inherited any order allowed, but here there is no reason. Just add 'common1' to the end. Rob