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Mon, 25 Apr 2022 23:05:14 +0200 Date: Mon, 25 Apr 2022 23:05:12 +0200 From: Jonathan =?utf-8?Q?Neusch=C3=A4fer?= To: Linus Walleij Subject: Re: [PATCH v5 04/11] clocksource/drivers: Add HPE GXP timer Message-ID: References: <20220421192132.109954-1-nick.hawkins@hpe.com> <20220421192132.109954-5-nick.hawkins@hpe.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="gPm3dkYWD93jriOi" Content-Disposition: inline In-Reply-To: X-Provags-ID: V03:K1:qHKJGgTrT6rptDoQmCaR5/ooQ1RbWgCkWERKZg4FKnl54DurbY9 /PnSE0q4TbnF4XcudxKc/bCV3O8Qi0qYwy9qngDLVe7dRMximXWDiF+Ll3EnffCQfA83zxr SgaLaLEgSMoG86Vtdvrk9JIeEM96kwXd/NlDB6b5khdILv5EDfhsdP5QtQ/jWkZ3jjOPHZ7 ObeA5vSZYNcml2YfaPYoA== X-UI-Out-Filterresults: notjunk:1;V03:K0:PfseJihy3hs=:wAvhC3gPVIPnGOBfUpDlKi HfiyVbUD324SxXk10UwRpeFnIh2RuU1xIlbVGIvY8nvfgmw+bZBZ1q2wpPbhPX8QObdLCFrWO vDlbSuq86UsSAQe0dfFr+rHRecoD3jImYjSSp0ZvYyFvraaGj1Hn2l5YX4V8OLjmjZvNv3h1M tYuSXff/NN+DLQD2zWuu6aROdBBJ4Gts9hHgpQbzNDWhjRBzwNT0KXNwEK4COfcdQDJnSh/Re 0xHRyslIa/2mFxUqqtnTZH8KZidSb26Lb5ZJh5KEOp2j+BBxZKtbjyLZlH1l0qSeUVbdoBtht ga9/awkOEJmYDqMPr9tCrNvf76ZdaRZu626gUZ2YsQjz4XQtJ+Zeha7LBV9bsiVvSNqv9vVvH G6rCqERyAKY0euWSmxP49wGHR4RMvu9kqYqFUmjop22PzGv8jJR6u/3COkrTgVEzv6LBm66sA ascFSEZPoFFp7fHUfYzU+Hb6OB+Q9qyvpYCLSJ7PEMNMF/xzxhJseoxJ7oHbcW4tFdKaBxv4M kfHyA0JvY6wSs/iE4M23tQzr6pEssbUiAIXLCGagYdIYqbhHOCEU22tBkg+XcDgv6wEyFR1kc I8v9iz4lueKaxynjURW/C018YhP0KhbUUEQ0HoPtj9989dm8kQAJ9wsWGz3owkHHvQd00mttz BUgdX/a45Yr9EIaA5/G4Z34r7MCjnRtiBoWruPZFwGvHtqkRurBicW3U8Uuf0njN7SZZ6U6D9 n3JLnm3FqfjxgXn1W1AZ8ShED+49xDdIVR6B5MrveS10pFXOxYH3orUQPN9X8rGANQteI6pAD 5SQ5f/2kY47skgwtE5K/kvnqpJc4KA5pp/SK/OsV3UcddGI2eB8nZ+sS9lz/caKFWAKgUTPjh x4WtXYNgyuJLq5kNaCIwrX4Q1pJJCBaoLn0fCgIFaDSKFs6FEZhvao02Til5xaL8h1gRiaPjK 9znX/6QN+0po9vOHKJ0ZcJksJv1drU9alJzniTZG5OeOmQZXWGJFNedEYFdeho53SBTndcDUc LACcAu7ba4+XojURIgBB1FJfp+Dr4HE4DHVf7QdHZgKO4mNdsEcLY0qzYO2Fl0mbw9JIzBxC7 meb5KClRPudfzI= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Arnd Bergmann , "Verdun, Jean-Marie" , Daniel Lezcano , Linux Kernel Mailing List , Joel Stanley , "Hawkins, Nick" , Thomas Gleixner , OpenBMC Maillist Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" --gPm3dkYWD93jriOi Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Apr 25, 2022 at 10:38:08PM +0200, Linus Walleij wrote: > On Fri, Apr 22, 2022 at 3:16 PM Arnd Bergmann wrote: [...] > The ixp4xx driver looks like that because the register range used for > the timer and the watchdog is combined, i.e. it is a single IP block: >=20 > timer@c8005000 { > compatible =3D "intel,ixp4xx-timer"; > reg =3D <0xc8005000 0x100>; > interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH>; > }; >=20 > Device tree probing does not allow two devices to probe from the same > DT node, so this was solved by letting the (less important) watchdog > be spawn as a platform device from the timer. >=20 > I don't know if double-probing for the same register range can be fixed, > but I was assuming that the one-compatible-to-one-driver assumption > was pretty hard-coded into the abstractions. Maybe it isn't? >=20 > Another way is of course to introduce an MFD. That becomes > problematic in another way: MFD abstractions are supposed to > be inbetween the resource and the devices it spawns, and with > timers/clocksources this creates a horrible special-casing since the > MFD bus (the parent may be providing e.g. an MMIO regmap) > then need to be early-populated and searched by the timer core > from TIMER_OF_DECLARE() early in boot. >=20 > So this solution was the lesser evil that I could think about. Nuvoton NPCM platforms use yet another approach: timer0: timer@8000 { compatible =3D "nuvoton,npcm750-timer"; interrupts =3D ; reg =3D <0x8000 0x1C>; clocks =3D <&clk NPCM7XX_CLK_TIMER>; }; watchdog0: watchdog@801C { compatible =3D "nuvoton,npcm750-wdt"; interrupts =3D ; reg =3D <0x801C 0x4>; status =3D "disabled"; clocks =3D <&clk NPCM7XX_CLK_TIMER>; }; The watchdog control register is in the same register block, but represented by a separate DT node. (not necessarily a recommendation, but it is another existing approach.) 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