From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: Re: [PATCH 2/4] mwait-idle: add SPR support
Date: Wed, 27 Apr 2022 13:39:52 +0200 [thread overview]
Message-ID: <YmkriORufeJv6Pel@Air-de-Roger> (raw)
In-Reply-To: <722833a9-e6bf-1a63-e866-aed0648c785e@suse.com>
On Tue, Apr 26, 2022 at 12:05:07PM +0200, Jan Beulich wrote:
> From: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
>
> Add Sapphire Rapids Xeon support.
>
> Up until very recently, the C1 and C1E C-states were independent, but this
> has changed in some new chips, including Sapphire Rapids Xeon (SPR). In these
> chips the C1 and C1E states cannot be enabled at the same time. The "C1E
> promotion" bit in 'MSR_IA32_POWER_CTL' also has its semantics changed a bit.
>
> Here are the C1, C1E, and "C1E promotion" bit rules on Xeons before SPR.
>
> 1. If C1E promotion bit is disabled.
> a. C1 requests end up with C1 C-state.
> b. C1E requests end up with C1E C-state.
> 2. If C1E promotion bit is enabled.
> a. C1 requests end up with C1E C-state.
> b. C1E requests end up with C1E C-state.
>
> Here are the C1, C1E, and "C1E promotion" bit rules on Sapphire Rapids Xeon.
> 1. If C1E promotion bit is disabled.
> a. C1 requests end up with C1 C-state.
> b. C1E requests end up with C1 C-state.
> 2. If C1E promotion bit is enabled.
> a. C1 requests end up with C1E C-state.
> b. C1E requests end up with C1E C-state.
>
> Before SPR Xeon, the 'intel_idle' driver was disabling C1E promotion and was
> exposing C1 and C1E as independent C-states. But on SPR, C1 and C1E cannot be
> enabled at the same time.
>
> This patch adds both C1 and C1E states. However, C1E is marked as with the
> "CPUIDLE_FLAG_UNUSABLE" flag, which means that in won't be registered by
> default. The C1E promotion bit will be cleared, which means that by default
> only C1 and C6 will be registered on SPR.
>
> The next patch will add an option for enabling C1E and disabling C1 on SPR.
>
> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 9edf3c0ffef0
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Roger Pau Monné <roger.pau@citrix.com>
Thanks, Roger.
next prev parent reply other threads:[~2022-04-27 11:40 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-26 10:03 [PATCH 0/4] x86/mwait-idle: (mostly) SPR support Jan Beulich
2022-04-26 10:04 ` [PATCH 1/4] x86/mwait-idle: switch to asm/intel-family.h naming Jan Beulich
2022-04-27 11:21 ` Roger Pau Monné
2022-04-26 10:05 ` [PATCH 2/4] mwait-idle: add SPR support Jan Beulich
2022-04-27 11:39 ` Roger Pau Monné [this message]
2022-04-26 10:05 ` [PATCH 3/4] mwait-idle: add 'preferred_cstates' module argument Jan Beulich
2022-04-27 12:45 ` Roger Pau Monné
2022-04-27 13:41 ` Jan Beulich
2022-04-27 15:06 ` Roger Pau Monné
2022-04-27 15:25 ` Jan Beulich
2022-04-27 16:12 ` Roger Pau Monné
2022-04-28 6:37 ` Jan Beulich
2022-04-28 8:06 ` Roger Pau Monné
2022-04-28 8:10 ` Jan Beulich
2022-04-26 10:06 ` [PATCH 4/4] mwait-idle: add core C6 optimization for SPR Jan Beulich
2022-04-27 12:56 ` Roger Pau Monné
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