Re: [Intel-gfx] [PATCH 04/11] drm/i915/pvc: Read correct RP_STATE_CAP register

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Mon, May 02, 2022 at 09:34:10AM -0700, Matt Roper wrote:
> The SoC registers, including RP_STATE_CAP, have moved to a new location
> in GTTMMADR on Ponte Vecchio.  We need to update the register offset
> accordingly.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++-
>  drivers/gpu/drm/i915/i915_reg.h     | 1 +
>  2 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 3476a11f294c..3bd8415a0f1b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1075,7 +1075,9 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
>  	struct drm_i915_private *i915 = rps_to_i915(rps);
>  	struct intel_uncore *uncore = rps_to_uncore(rps);
>  
> -	if (IS_XEHPSDV(i915))
> +	if (IS_PONTEVECCHIO(i915))
> +		return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
> +	else if (IS_XEHPSDV(i915))
>  		return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);
>  	else if (IS_GEN9_LP(i915))
>  		return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9ccb67eec1bd..4a3d7b96ef43 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1846,6 +1846,7 @@
>  #define BXT_RP_STATE_CAP        _MMIO(0x138170)
>  #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
>  #define XEHPSDV_RP_STATE_CAP	_MMIO(0x250014)
> +#define PVC_RP_STATE_CAP	_MMIO(0x281014)
>  
>  #define GT0_PERF_LIMIT_REASONS		_MMIO(0x1381a8)
>  #define   GT0_PERF_LIMIT_REASONS_MASK	0xde3
> -- 
> 2.35.1
>