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From: Catalin Marinas <catalin.marinas@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 00/12] arm64: Automatic system register definition generation
Date: Wed, 4 May 2022 17:17:12 +0100	[thread overview]
Message-ID: <YnKnCCk3f2CPoyQZ@arm.com> (raw)
In-Reply-To: <20220503170233.507788-1-broonie@kernel.org>

On Tue, May 03, 2022 at 06:02:21PM +0100, Mark Brown wrote:
> This patch series introduces a
> script which describes registers and the fields within them in a format
> that is easy to cross reference with the architecture reference manual
> and uses them to generate the constants we use in a standard format:

Something went wrong since v5, likely some encoding is wrong:

kvm [1]: sys_reg table (____ptrval____) out of order (138)
------------[ cut here ]------------
kernel BUG at arch/arm64/kvm/sys_regs.c:2869!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
Modules linked in:
CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.18.0-rc3-00012-g0cabf2a94034 #1
Hardware name: QEMU QEMU Virtual Machine, BIOS 0.0.0 02/06/2015
pstate: 62400005 (nZCv daif +PAN -UAO +TCO -DIT -SSBS BTYPE=--)
pc : kvm_sys_reg_table_init+0x138/0x170
lr : kvm_sys_reg_table_init+0x24/0x170
sp : ffff80000801bc90
x29: ffff80000801bc90 x28: 0000000000000000 x27: 0000000000000001
x26: 0000000000000e58 x25: 0000000000000100 x24: 0000000000000004
x23: ffffa2429433d000 x22: ffffa24294879a38 x21: ffffa24294879c80
x20: ffffa24294879a58 x19: ffffa24294bb65e8 x18: ffffffffffffffff
x17: 0000000000000003 x16: 00000000000001f7 x15: ffff80008801b9a7
x14: 0000000000000000 x13: ffffa242948924a0 x12: 0000000000000285
x11: 00000000000000d7 x10: ffffa242948ea4a0 x9 : ffffa242948924a0
x8 : 00000000ffffefff x7 : ffffa242948ea4a0 x6 : 0000000000000000
x5 : 000000000000bff4 x4 : 0000000000000000 x3 : 0000000000000000
x2 : 0000000000000000 x1 : ffff000000088000 x0 : 0000000000000001
Call trace:
 kvm_sys_reg_table_init+0x138/0x170
 kvm_arch_init+0x904/0xd70
 kvm_init+0x38/0x3a4
 arm_init+0x20/0x30
 do_one_initcall+0x50/0x1c0
 kernel_init_freeable+0x208/0x28c
 kernel_init+0x28/0x13c
 ret_from_fork+0x10/0x20

-- 
Catalin

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  parent reply	other threads:[~2022-05-04 16:18 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03 17:02 [PATCH v6 00/12] arm64: Automatic system register definition generation Mark Brown
2022-05-03 17:02 ` [PATCH v6 01/12] arm64/sysreg: Introduce helpers for access to sysreg fields Mark Brown
2022-05-03 17:02 ` [PATCH v6 02/12] arm64/mte: Make TCF0 naming and field values more standard Mark Brown
2022-05-03 17:02 ` [PATCH v6 03/12] arm64/mte: Make TCF field values and naming " Mark Brown
2022-05-04 13:26   ` Mark Rutland
2022-05-03 17:02 ` [PATCH v6 04/12] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-05-03 17:02 ` [PATCH v6 05/12] arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1 Mark Brown
2022-05-04 13:35   ` Mark Rutland
2022-05-03 17:02 ` [PATCH v6 06/12] arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM Mark Brown
2022-05-03 17:02 ` [PATCH v6 07/12] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-05-03 17:02 ` [PATCH v6 08/12] arm64: Add sysreg header generation scripting Mark Brown
2022-05-03 17:02 ` [PATCH v6 09/12] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-05-03 17:02 ` [PATCH v6 10/12] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-05-03 17:02 ` [PATCH v6 11/12] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-05-03 17:02 ` [PATCH v6 12/12] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-05-04 16:32   ` Mark Rutland
2022-05-04 16:40     ` Mark Brown
2022-05-04 17:56       ` Catalin Marinas
2022-05-04 16:17 ` Catalin Marinas [this message]
2022-05-04 19:58 ` [PATCH v6 00/12] arm64: Automatic system register definition generation Catalin Marinas

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