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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id a11-20020a05680802cb00b00325cda1ff93sm18331oid.18.2022.05.04.14.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 14:30:00 -0700 (PDT) Received: (nullmailer pid 2258214 invoked by uid 1000); Wed, 04 May 2022 21:29:59 -0000 Date: Wed, 4 May 2022 16:29:59 -0500 From: Rob Herring To: Biju Das Cc: Thierry Reding , Lee Jones , Krzysztof Kozlowski , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org Subject: Re: [RFC 1/5] dt-bindings: pwm: Add RZ/G2L GPT binding Message-ID: References: <20220430075915.5036-1-biju.das.jz@bp.renesas.com> <20220430075915.5036-2-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220430075915.5036-2-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org On Sat, Apr 30, 2022 at 08:59:11AM +0100, Biju Das wrote: > Add device tree bindings for the RZ/G2L General PWM Timer (GPT). > > Signed-off-by: Biju Das > --- > .../bindings/pwm/renesas,rzg2l-gpt.yaml | 104 ++++++++++++++++++ > 1 file changed, 104 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > new file mode 100644 > index 000000000000..0e44c0fbe04a > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > @@ -0,0 +1,104 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L General PWM Timer (GPT) > + > +maintainers: > + - Biju Das > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a07g044-gpt # RZ/G2{L,LC} > + - renesas,r9a07g054-gpt # RZ/V2L > + - const: renesas,rzg2l-gpt > + > + reg: > + # base address and length of the registers block for the PWM. Yes, that's all 'reg', drop. > + maxItems: 1 > + > + '#pwm-cells': > + # should be 2. See pwm.yaml in this directory for a description of > + # the cells format. 2 cells the schema says already. The reference for the format is okay, but move it to a 'description' entry. > + const: 2 > + > + interrupts: > + items: > + - description: GTCCRA input capture/compare match > + - description: GTCCRB input capture/compare > + - description: GTCCRC compare match > + - description: GTCCRD compare match > + - description: GTCCRE compare match > + - description: GTCCRF compare match > + - description: GTADTRA compare match > + - description: GTADTRB compare match > + - description: GTCNT overflow/GTPR compare match > + - description: GTCNT underflow > + > + interrupt-names: > + items: > + - const: ccmpa > + - const: ccmpb > + - const: cmpc > + - const: cmpd > + - const: cmpe > + - const: cmpf > + - const: adtrga > + - const: adtrgb > + - const: ovf > + - const: unf > + > + clocks: > + # clock phandle and specifier pair. That's all 'clocks', drop. > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + - power-domains > + - resets > + > +allOf: > + - $ref: pwm.yaml# > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + gpt4: pwm@10048400 { > + compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt"; > + reg = <0x10048400 0xa4>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", > + "cmpe", "cmpf", "adtrga", "adtrgb", > + "ovf", "unf"; > + clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>; > + power-domains = <&cpg>; > + resets = <&cpg 523 R9A07G044_GPT_RST_C>; > + #pwm-cells = <2>; > + }; > -- > 2.25.1 > >