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diff for duplicates of <YnPZUFgZHJ9mFe0D@robh.at.kernel.org>

diff --git a/a/1.txt b/N1/1.txt
index 99b2f57..c43d667 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -61,7 +61,7 @@ On Thu, Apr 07, 2022 at 11:54:16AM +0530, Sumit Gupta wrote:
 > > > > > > > +
 > > > > > > > +examples:
 > > > > > > > +  - |
-> > > > > > > +    axi2apb: axi2apb@2390000 {
+> > > > > > > +    axi2apb: axi2apb(a)2390000 {
 > > > > > > As axi2apb appears to be a bus, then all the child nodes (APB devices)
 > > > > > > should be under this node.
 > > > > > axi2apb is a bridge which coverts an AXI to APB interface
@@ -71,7 +71,7 @@ On Thu, Apr 07, 2022 at 11:54:16AM +0530, Sumit Gupta wrote:
 > > > > example.
 > > > Sorry for taking so long to reply, this fell through the cracks.
 > > > 
-> > > These aren't really bridges as such. CBB (which we call /bus@0 in DT) is
+> > > These aren't really bridges as such. CBB (which we call /bus(a)0 in DT) is
 > > > a sort of large container for all IP. Within that there are various shim
 > > > layers that connect these "legacy" interfaces to CBB. I suppose you
 > > > could call them bridges, but it's a bit of a stretch. From a software
@@ -84,7 +84,7 @@ On Thu, Apr 07, 2022 at 11:54:16AM +0530, Sumit Gupta wrote:
 > > > My understanding is that this is also gone in newer chips, so matters
 > > > become a bit simpler there.
 > > > 
-> > > Reorganizing /bus@0 into multiple bridges and busses would be a lot of
+> > > Reorganizing /bus(a)0 into multiple bridges and busses would be a lot of
 > > > churn and likely confuse people that want to correlate what's in the TRM
 > > > to what's in DT, so I don't think it's worth it.
 > > > 
diff --git a/a/content_digest b/N1/content_digest
index b6b2e5f..a8d05df 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,26 +1,9 @@
- "ref\020211221125117.6545-1-sumitg@nvidia.com\0"
- "ref\020211221125117.6545-4-sumitg@nvidia.com\0"
- "ref\0YcNv7xm19sFTlfjW@robh.at.kernel.org\0"
- "ref\0226fd57c-2631-ec7a-fc48-d6547d557681@nvidia.com\0"
- "ref\0CAL_Jsq+=hGG-cMwvM0sKFW=Rwa56=fqS379jL4ZjSyDKOia-RA@mail.gmail.com\0"
- "ref\0YhY1Hhgz/O724oYL@orome\0"
- "ref\0e1d484b5-b755-e406-8711-62f3756759f3@nvidia.com\0"
  "ref\02713db35-927b-c3de-20ba-fb9c613c9291@nvidia.com\0"
  "From\0Rob Herring <robh@kernel.org>\0"
  "Subject\0Re: [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding\0"
- "Date\0Thu, 5 May 2022 09:04:00 -0500\0"
- "To\0Sumit Gupta <sumitg@nvidia.com>\0"
- "Cc\0Thierry Reding <thierry.reding@gmail.com>"
-  linux-tegra <linux-tegra@vger.kernel.org>
-  linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>
-  devicetree@vger.kernel.org
-  Jon Hunter <jonathanh@nvidia.com>
-  kbuild-all@lists.01.org
-  bbasu@nvidia.com
-  vsethi@nvidia.com
-  jsequeira@nvidia.com
- " Thierry Reding <treding@nvidia.com>\0"
- "\00:1\0"
+ "Date\0Thu, 05 May 2022 09:04:00 -0500\0"
+ "To\0kbuild-all@lists.01.org\0"
+ "\01:1\0"
  "b\0"
  "On Thu, Apr 07, 2022 at 11:54:16AM +0530, Sumit Gupta wrote:\n"
  "> \n"
@@ -85,7 +68,7 @@
  "> > > > > > > +\n"
  "> > > > > > > +examples:\n"
  "> > > > > > > +\302\240 - |\n"
- "> > > > > > > +\302\240\302\240\302\240 axi2apb: axi2apb@2390000 {\n"
+ "> > > > > > > +\302\240\302\240\302\240 axi2apb: axi2apb(a)2390000 {\n"
  "> > > > > > As axi2apb appears to be a bus, then all the child nodes (APB devices)\n"
  "> > > > > > should be under this node.\n"
  "> > > > > axi2apb is a bridge which coverts an AXI to APB interface\n"
@@ -95,7 +78,7 @@
  "> > > > example.\n"
  "> > > Sorry for taking so long to reply, this fell through the cracks.\n"
  "> > > \n"
- "> > > These aren't really bridges as such. CBB (which we call /bus@0 in DT) is\n"
+ "> > > These aren't really bridges as such. CBB (which we call /bus(a)0 in DT) is\n"
  "> > > a sort of large container for all IP. Within that there are various shim\n"
  "> > > layers that connect these \"legacy\" interfaces to CBB. I suppose you\n"
  "> > > could call them bridges, but it's a bit of a stretch. From a software\n"
@@ -108,7 +91,7 @@
  "> > > My understanding is that this is also gone in newer chips, so matters\n"
  "> > > become a bit simpler there.\n"
  "> > > \n"
- "> > > Reorganizing /bus@0 into multiple bridges and busses would be a lot of\n"
+ "> > > Reorganizing /bus(a)0 into multiple bridges and busses would be a lot of\n"
  "> > > churn and likely confuse people that want to correlate what's in the TRM\n"
  "> > > to what's in DT, so I don't think it's worth it.\n"
  "> > > \n"
@@ -134,4 +117,4 @@
  "\n"
  Rob
 
-49069ac15a37a74e7d8d6c30ae234eb6494c12e1db554a35c4ad0e2198dce764
+12613a1110000bc2ba9a82643d88e970f01485cb95beb5e89a45ec40fe8c47b7

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