From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41A54C433EF for ; Thu, 12 May 2022 00:30:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=V+aMOUw0Y8KTfXDCqTZWkL52Ny1zGNbcMqyTqgsOFBw=; b=wymZaKjofbbUrY /ZGrbYf5AW0oPvTJ264AtvfnTo+fMFGGyfHjCKVmBdm1CPLjS2fxx38d96mCm8siIY27nCS8x7n5f pZ48aroLuoS65DYZfv1FDOAD7pVBHNdP+VtNYxS4tyzwOM22mjc9R2Q8o9nBomkdCEVkvEXpxSqtu scR96bwNw1URmbGBvrCq/n5/xGQ8eSeblzubRQSTO8q8W5rXPJZqRc/XNBFHlHLBIWjlhCqp66+p6 9kaJpYfgyji0ucCSqVEPUJPglMRimHa+TlNFjj973mjnzNczODCQkxdAUm2EoOGWXELp2rvZvu1j2 lWUhxiUvQ0iqX25uxkiw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nowh5-00996X-C4; Thu, 12 May 2022 00:28:39 +0000 Received: from vps0.lunn.ch ([185.16.172.187]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nowh2-00995N-FR for linux-arm-kernel@lists.infradead.org; Thu, 12 May 2022 00:28:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=JQQpXDILRhi5lJijLn3ENVGB5zi9S0zGMEw13K7gPKk=; b=blQpV2LjsgKnCKs0TW01z5Mbf0 oosEGMaHooVxuB5o+XTXzqenvcUp+3IdvMLDGqHM5zTxXIA22z2i07aMFUJ73a/ZLp9jjjMvalBk9 ErAfLohHDRErOuVrWafejakN50eHMlryhbzlq9dGx72qjBDr/g8VzFy7Bo50GhShJZrs=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1nowfw-002N8s-Ru; Thu, 12 May 2022 02:27:28 +0200 Date: Thu, 12 May 2022 02:27:28 +0200 From: Andrew Lunn To: Chris Packham Cc: "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "gregory.clement@bootlin.com" , "sebastian.hesselbarth@gmail.com" , "kostap@marvell.com" , "robert.marko@sartura.hr" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles Message-ID: References: <20220510231002.1160798-1-chris.packham@alliedtelesis.co.nz> <20220510231002.1160798-2-chris.packham@alliedtelesis.co.nz> <608a7d9d-9238-281a-8770-aa20feb7e6be@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <608a7d9d-9238-281a-8770-aa20feb7e6be@alliedtelesis.co.nz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220511_172836_553355_096CB1B7 X-CRM114-Status: GOOD ( 18.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 11, 2022 at 11:14:25PM +0000, Chris Packham wrote: > > On 12/05/22 05:02, Andrew Lunn wrote: > > On Wed, May 11, 2022 at 11:10:00AM +1200, Chris Packham wrote: > >> Describe the compatible properties for the Marvell Alleycat5/5X switches > >> with integrated CPUs. > >> > >> Alleycat5: > >> * 98DX2538: 24x1G + 2x10G + 2x10G Stack > >> * 98DX2535: 24x1G + 4x1G Stack > >> * 98DX2532: 8x1G + 2x10G + 2x1G Stack > >> * 98DX2531: 8x1G + 4x1G Stack > >> * 98DX2528: 24x1G + 2x10G + 2x10G Stack > >> * 98DX2525: 24x1G + 4x1G Stack > >> * 98DX2522: 8x1G + 2x10G + 2x1G Stack > >> * 98DX2521: 8x1G + 4x1G Stack > >> * 98DX2518: 24x1G + 2x10G + 2x10G Stack > >> * 98DX2515: 24x1G + 4x1G Stack > >> * 98DX2512: 8x1G + 2x10G + 2x1G Stack > >> * 98DX2511: 8x1G + 4x1G Stack > >> > >> Alleycat5X: > >> * 98DX3500: 24x1G + 6x25G > >> * 98DX3501: 16x1G + 6x10G > >> * 98DX3510: 48x1G + 6x25G > >> * 98DX3520: 24x2.5G + 6x25G > >> * 98DX3530: 48x2.5G + 6x25G > >> * 98DX3540: 12x5G/6x10G + 6x25G > >> * 98DX3550: 24x5G/12x10G + 6x25G > > Hi Chris > > > > When looking at this list, is it just the switch which changes, and > > everything else in the package stays the same? > > CPU wise I've been told everything is identical. The differences are all > in the switch side. O.K. That helps a lot with this description. > > armada-98DX2538.dtsi which extends armada-98DX25xx.dtsi > > There wouldn't be anything to add in 98DX2538 (at least not until we > have a proper switchdev driver). Does the switch/SoC have ID registers? For mv88e6xxx, the switch is identified by its ID registers, so we don't have switch specific compatible value in DT. Hopefully it is the same here. All we need to say is that there is a switch in the main .dtsi file, and the .dts file would then indicate which ports are actually used. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 587D2C433F5 for ; Thu, 12 May 2022 00:28:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349654AbiELA2h (ORCPT ); Wed, 11 May 2022 20:28:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349655AbiELA2h (ORCPT ); Wed, 11 May 2022 20:28:37 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAD221AEC69; Wed, 11 May 2022 17:28:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=JQQpXDILRhi5lJijLn3ENVGB5zi9S0zGMEw13K7gPKk=; b=blQpV2LjsgKnCKs0TW01z5Mbf0 oosEGMaHooVxuB5o+XTXzqenvcUp+3IdvMLDGqHM5zTxXIA22z2i07aMFUJ73a/ZLp9jjjMvalBk9 ErAfLohHDRErOuVrWafejakN50eHMlryhbzlq9dGx72qjBDr/g8VzFy7Bo50GhShJZrs=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1nowfw-002N8s-Ru; Thu, 12 May 2022 02:27:28 +0200 Date: Thu, 12 May 2022 02:27:28 +0200 From: Andrew Lunn To: Chris Packham Cc: "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "gregory.clement@bootlin.com" , "sebastian.hesselbarth@gmail.com" , "kostap@marvell.com" , "robert.marko@sartura.hr" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles Message-ID: References: <20220510231002.1160798-1-chris.packham@alliedtelesis.co.nz> <20220510231002.1160798-2-chris.packham@alliedtelesis.co.nz> <608a7d9d-9238-281a-8770-aa20feb7e6be@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <608a7d9d-9238-281a-8770-aa20feb7e6be@alliedtelesis.co.nz> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, May 11, 2022 at 11:14:25PM +0000, Chris Packham wrote: > > On 12/05/22 05:02, Andrew Lunn wrote: > > On Wed, May 11, 2022 at 11:10:00AM +1200, Chris Packham wrote: > >> Describe the compatible properties for the Marvell Alleycat5/5X switches > >> with integrated CPUs. > >> > >> Alleycat5: > >> * 98DX2538: 24x1G + 2x10G + 2x10G Stack > >> * 98DX2535: 24x1G + 4x1G Stack > >> * 98DX2532: 8x1G + 2x10G + 2x1G Stack > >> * 98DX2531: 8x1G + 4x1G Stack > >> * 98DX2528: 24x1G + 2x10G + 2x10G Stack > >> * 98DX2525: 24x1G + 4x1G Stack > >> * 98DX2522: 8x1G + 2x10G + 2x1G Stack > >> * 98DX2521: 8x1G + 4x1G Stack > >> * 98DX2518: 24x1G + 2x10G + 2x10G Stack > >> * 98DX2515: 24x1G + 4x1G Stack > >> * 98DX2512: 8x1G + 2x10G + 2x1G Stack > >> * 98DX2511: 8x1G + 4x1G Stack > >> > >> Alleycat5X: > >> * 98DX3500: 24x1G + 6x25G > >> * 98DX3501: 16x1G + 6x10G > >> * 98DX3510: 48x1G + 6x25G > >> * 98DX3520: 24x2.5G + 6x25G > >> * 98DX3530: 48x2.5G + 6x25G > >> * 98DX3540: 12x5G/6x10G + 6x25G > >> * 98DX3550: 24x5G/12x10G + 6x25G > > Hi Chris > > > > When looking at this list, is it just the switch which changes, and > > everything else in the package stays the same? > > CPU wise I've been told everything is identical. The differences are all > in the switch side. O.K. That helps a lot with this description. > > armada-98DX2538.dtsi which extends armada-98DX25xx.dtsi > > There wouldn't be anything to add in 98DX2538 (at least not until we > have a proper switchdev driver). Does the switch/SoC have ID registers? For mv88e6xxx, the switch is identified by its ID registers, so we don't have switch specific compatible value in DT. Hopefully it is the same here. All we need to say is that there is a switch in the main .dtsi file, and the .dts file would then indicate which ports are actually used. Andrew