From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BF8AC433F5 for ; Thu, 12 May 2022 00:46:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RgF2PDS6LCMSAarQeVQAu8SiHA2znsmY+FNQMCSKbLc=; b=Rk5tQkW049fABw 5Be0BEBUcAXoH/QPv/S5DO4TKqR0Hltv8vRYA111TNhPVRckc7wVczSnyYFoZBWPpnqidfCGEXw8H bRn6I9vEDrw0cCHcGh40EBrnm1HjMx8J0KhcRbIhrK7KyZATiumRh56w7mEP/iH3kj5foKgiDSq4s iucj2XdNPqWegkx+uxneR2FRLMTd4VFhBJodzkF29g+eM5Crzp/TuSV/mQ/AUYgMZJ3hHOTtwx1Bj vmFXCTBPuE8bZI/+mWrWKzQxQ/GNmK14iWgO8aT8oeQh3ME2npr7GeiZZK6hfk7UjSb1T2UsQkw76 dBYYxVMqdQ7tgCcGrt1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nowxm-009AoG-Le; Thu, 12 May 2022 00:45:54 +0000 Received: from vps0.lunn.ch ([185.16.172.187]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nowxk-009AnY-Gj for linux-arm-kernel@lists.infradead.org; Thu, 12 May 2022 00:45:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=P3j6JNTPki/LW6Lx+K5sl1l625zeCFl9dehtVEycpws=; b=piM4VjBx/IAEu2/eYZ6g+T+qHT N0eed6UnxXniHjZ8UQol6BGPhCg+C571Ka74nRLhzOzyL6xLngCwU0uvwndGF0T/Ou1gHPzcvhkko 9HPJqtAwJTqyusDFoUHn1QyJ7yXw//NqqZDluAkt/QHeIYGES7tWqiR4pZlozQwKiMn0=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1nowxY-002NEV-GU; Thu, 12 May 2022 02:45:40 +0200 Date: Thu, 12 May 2022 02:45:40 +0200 From: Andrew Lunn To: Chris Packham Cc: "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "gregory.clement@bootlin.com" , "sebastian.hesselbarth@gmail.com" , "kostap@marvell.com" , "robert.marko@sartura.hr" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles Message-ID: References: <20220510231002.1160798-1-chris.packham@alliedtelesis.co.nz> <20220510231002.1160798-2-chris.packham@alliedtelesis.co.nz> <608a7d9d-9238-281a-8770-aa20feb7e6be@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220511_174552_587764_D428D859 X-CRM114-Status: GOOD ( 10.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > Yes there are registers that you can read to identify the specific chip. > > It still might be useful to have a expected vs actual check as those ID > values are determined by pin strapping resistors. That i don't get? Can i turn a * 98DX2538: 24x1G + 2x10G + 2x10G Stack into a * 98DX2535: 24x1G + 4x1G Stack by strapping its pin differently? > It could also be used > to validate the dts (e.g. port 20 would be invalid on a 98DX3501). But > those are considerations for further down the track. Yes, that would be up to the switchdev driver to validate the DT based on the ID register. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C3B3C433F5 for ; Thu, 12 May 2022 00:46:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349749AbiELAp7 (ORCPT ); Wed, 11 May 2022 20:45:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345699AbiELApv (ORCPT ); Wed, 11 May 2022 20:45:51 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF5711AD82; Wed, 11 May 2022 17:45:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=P3j6JNTPki/LW6Lx+K5sl1l625zeCFl9dehtVEycpws=; b=piM4VjBx/IAEu2/eYZ6g+T+qHT N0eed6UnxXniHjZ8UQol6BGPhCg+C571Ka74nRLhzOzyL6xLngCwU0uvwndGF0T/Ou1gHPzcvhkko 9HPJqtAwJTqyusDFoUHn1QyJ7yXw//NqqZDluAkt/QHeIYGES7tWqiR4pZlozQwKiMn0=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1nowxY-002NEV-GU; Thu, 12 May 2022 02:45:40 +0200 Date: Thu, 12 May 2022 02:45:40 +0200 From: Andrew Lunn To: Chris Packham Cc: "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "gregory.clement@bootlin.com" , "sebastian.hesselbarth@gmail.com" , "kostap@marvell.com" , "robert.marko@sartura.hr" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles Message-ID: References: <20220510231002.1160798-1-chris.packham@alliedtelesis.co.nz> <20220510231002.1160798-2-chris.packham@alliedtelesis.co.nz> <608a7d9d-9238-281a-8770-aa20feb7e6be@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org > Yes there are registers that you can read to identify the specific chip. > > It still might be useful to have a expected vs actual check as those ID > values are determined by pin strapping resistors. That i don't get? Can i turn a * 98DX2538: 24x1G + 2x10G + 2x10G Stack into a * 98DX2535: 24x1G + 4x1G Stack by strapping its pin differently? > It could also be used > to validate the dts (e.g. port 20 would be invalid on a 98DX3501). But > those are considerations for further down the track. Yes, that would be up to the switchdev driver to validate the DT based on the ID register. Andrew