From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Cc: Shyam-sundar.S-k@amd.com, linus.walleij@linaro.org,
linux-gpio@vger.kernel.org, mika.westerberg@linux.intel.com
Subject: Re: [PATCH v3 3/6] pinctrl: amd: Use PINCTRL_GRP to manage pingroups
Date: Tue, 31 May 2022 13:22:13 +0300 [thread overview]
Message-ID: <YpXsVSBt89N5BwfB@smile.fi.intel.com> (raw)
In-Reply-To: <20220531084322.1310250-4-Basavaraj.Natikar@amd.com>
On Tue, May 31, 2022 at 02:13:19PM +0530, Basavaraj Natikar wrote:
> AMD pingroup can be extended to support multi-function pins.
> Hence use PINCTRL_GRP to manage and represent larger number
> of pingroups inline.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
(with comments addressed in patch 1 and this one changed accordingly)
> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
> ---
> drivers/pinctrl/pinctrl-amd.h | 36 ++++++-----------------------------
> 1 file changed, 6 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h
> index 551dfa664ed8..d47217e7b39f 100644
> --- a/drivers/pinctrl/pinctrl-amd.h
> +++ b/drivers/pinctrl/pinctrl-amd.h
> @@ -291,36 +291,12 @@ static const unsigned uart0_pins[] = {135, 136, 137, 138, 139};
> static const unsigned uart1_pins[] = {140, 141, 142, 143, 144};
>
> static const struct pingroup kerncz_groups[] = {
> - {
> - .name = "i2c0",
> - .pins = i2c0_pins,
> - .npins = 2,
> - },
> - {
> - .name = "i2c1",
> - .pins = i2c1_pins,
> - .npins = 2,
> - },
> - {
> - .name = "i2c2",
> - .pins = i2c2_pins,
> - .npins = 2,
> - },
> - {
> - .name = "i2c3",
> - .pins = i2c3_pins,
> - .npins = 2,
> - },
> - {
> - .name = "uart0",
> - .pins = uart0_pins,
> - .npins = 5,
> - },
> - {
> - .name = "uart1",
> - .pins = uart1_pins,
> - .npins = 5,
> - },
> + PINCTRL_GRP("i2c0", i2c0_pins, 2),
> + PINCTRL_GRP("i2c1", i2c1_pins, 2),
> + PINCTRL_GRP("i2c2", i2c2_pins, 2),
> + PINCTRL_GRP("i2c3", i2c3_pins, 2),
> + PINCTRL_GRP("uart0", uart0_pins, 5),
> + PINCTRL_GRP("uart1", uart1_pins, 5),
> };
>
> #endif
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2022-05-31 10:22 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-31 8:43 [PATCH v3 0/6] Enhancements to AMD pinctrl and implementation of AMD pinmux Basavaraj Natikar
2022-05-31 8:43 ` [PATCH v3 1/6] pinctrl: Add pingroup and define PINCTRL_GRP Basavaraj Natikar
2022-05-31 9:19 ` Andy Shevchenko
2022-05-31 14:05 ` Basavaraj Natikar
2022-05-31 18:47 ` Andy Shevchenko
2022-05-31 8:43 ` [PATCH v3 2/6] pinctrl: amd: Remove amd_pingroup and use pingroup Basavaraj Natikar
2022-05-31 10:21 ` Andy Shevchenko
2022-05-31 8:43 ` [PATCH v3 3/6] pinctrl: amd: Use PINCTRL_GRP to manage pingroups Basavaraj Natikar
2022-05-31 10:22 ` Andy Shevchenko [this message]
2022-05-31 8:43 ` [PATCH v3 4/6] pinctrl: amd: Define and use AMD_PINS macro Basavaraj Natikar
2022-05-31 10:23 ` Andy Shevchenko
2022-05-31 13:58 ` Basavaraj Natikar
2022-05-31 15:47 ` Andy Shevchenko
2022-05-31 8:43 ` [PATCH v3 5/6] pinctrl: amd: Add amd_get_iomux_res function Basavaraj Natikar
2022-05-31 10:26 ` Andy Shevchenko
2022-05-31 8:43 ` [PATCH v3 6/6] pinctrl: amd: Implement pinmux functionality Basavaraj Natikar
2022-05-31 10:32 ` Andy Shevchenko
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