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From: Johan Hovold <johan@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Vinod Koul <vkoul@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v12 3/8] PCI: dwc: Convert msi_irq to the array
Date: Thu, 2 Jun 2022 15:45:59 +0200	[thread overview]
Message-ID: <Ypi/F/3XdpDo4cfY@hovoldconsulting.com> (raw)
In-Reply-To: <20220523181836.2019180-4-dmitry.baryshkov@linaro.org>

On Mon, May 23, 2022 at 09:18:31PM +0300, Dmitry Baryshkov wrote:
> Qualcomm version of DWC PCIe controller supports more than 32 MSI
> interrupts, but they are routed to separate interrupts in groups of 32
> vectors. To support such configuration, change the msi_irq field into an
> array. Let the DWC core handle all interrupts that were set in this
> array.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/pci/controller/dwc/pci-dra7xx.c       |  2 +-
>  drivers/pci/controller/dwc/pci-exynos.c       |  2 +-
>  .../pci/controller/dwc/pcie-designware-host.c | 30 +++++++++++--------
>  drivers/pci/controller/dwc/pcie-designware.h  |  2 +-
>  drivers/pci/controller/dwc/pcie-keembay.c     |  2 +-
>  drivers/pci/controller/dwc/pcie-spear13xx.c   |  2 +-
>  drivers/pci/controller/dwc/pcie-tegra194.c    |  2 +-
>  7 files changed, 24 insertions(+), 18 deletions(-)

> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index af91fe69f542..8dd913f69de7 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -257,8 +257,11 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
>  
>  static void dw_pcie_free_msi(struct pcie_port *pp)
>  {
> -	if (pp->msi_irq > 0)
> -		irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
> +	u32 ctrl;
> +
> +	for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
> +		if (pp->msi_irq[ctrl] > 0)
> +			irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL);

I'd use brackets around multline statements for readability.

>  	irq_domain_remove(pp->msi_domain);
>  	irq_domain_remove(pp->irq_domain);

> @@ -383,10 +388,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  			if (ret)
>  				return ret;
>  
> -			if (pp->msi_irq > 0)
> -				irq_set_chained_handler_and_data(pp->msi_irq,
> -							    dw_chained_msi_isr,
> -							    pp);
> +			for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> +				if (pp->msi_irq[ctrl] > 0)
> +					irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
> +									 dw_chained_msi_isr,
> +									 pp);

Same here (even if the old code didn't use it).

>  			ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
>  			if (ret)

Looks good otherwise.

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

Johan

  parent reply	other threads:[~2022-06-02 13:46 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-23 18:18 [PATCH v12 0/8] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-05-23 18:18 ` [PATCH v12 1/8] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Dmitry Baryshkov
2022-05-23 18:18 ` [PATCH v12 2/8] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-06-02 13:42   ` Johan Hovold
2022-05-23 18:18 ` [PATCH v12 3/8] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
2022-05-26 18:05   ` Rob Herring
2022-06-02 13:45   ` Johan Hovold [this message]
2022-05-23 18:18 ` [PATCH v12 4/8] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
2022-05-26 18:09   ` Rob Herring
2022-05-26 20:57     ` Dmitry Baryshkov
2022-06-02 13:55   ` Johan Hovold
2022-05-23 18:18 ` [PATCH v12 5/8] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-05-26 18:17   ` Rob Herring
2022-06-02 14:18   ` Johan Hovold
2022-05-23 18:18 ` [PATCH v12 6/8] PCI: dwc: Implement special ISR handler for split MSI IRQ setup Dmitry Baryshkov
2022-05-24  0:18   ` kernel test robot
2022-05-26 18:42   ` Rob Herring
2022-05-26 20:29     ` Dmitry Baryshkov
2022-05-23 18:18 ` [PATCH v12 7/8] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-05-26 18:19   ` Rob Herring
2022-05-23 18:18 ` [PATCH v12 8/8] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
2022-05-24 14:52 ` [PATCH v12 0/8] PCI: qcom: Fix higher MSI vectors handling Bjorn Helgaas
2022-05-24 16:17   ` Dmitry Baryshkov
2022-05-24 16:35     ` Bjorn Helgaas
2022-06-02 14:21 ` Johan Hovold

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