From: Klaus Jensen <its@irrelevant.dk>
To: Lukasz Maniak <lukasz.maniak@linux.intel.com>
Cc: qemu-devel@nongnu.org, Keith Busch <kbusch@kernel.org>,
qemu-block@nongnu.org, Klaus Jensen <k.jensen@samsung.com>,
lukasz.gieryk@linux.intel.com
Subject: Re: [PATCH v2] hw/nvme: clean up CC register write logic
Date: Fri, 3 Jun 2022 22:24:51 +0200 [thread overview]
Message-ID: <YppuEyXp/iL06z/C@apples> (raw)
In-Reply-To: <YpdpjLHhJDpTn7kP@kzawora-mobl.ger.corp.intel.com>
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On Jun 1 15:28, Lukasz Maniak wrote:
> On Wed, May 25, 2022 at 09:35:24AM +0200, Klaus Jensen wrote:
> >
> > + stl_le_p(&n->bar.intms, 0);
> > + stl_le_p(&n->bar.intmc, 0);
> > + stl_le_p(&n->bar.cc, 0);
>
> Looks fine, though it seems the NVMe spec says the above registers
> should be cleared during each reset for VF as well.
>
Aren't the values of all other registers than CSTS just undefined? (NVMe
v2.0b, Section 8.26.3)
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next prev parent reply other threads:[~2022-06-03 20:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-25 7:35 [PATCH v2] hw/nvme: clean up CC register write logic Klaus Jensen
2022-06-01 13:28 ` Lukasz Maniak
2022-06-03 20:24 ` Klaus Jensen [this message]
2022-06-07 11:06 ` Łukasz Gieryk
2022-06-07 11:23 ` Klaus Jensen
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