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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id u7-20020a63b547000000b003fc136f9a7dsm5649504pgo.38.2022.06.13.09.41.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 09:41:31 -0700 (PDT) Date: Mon, 13 Jun 2022 16:41:27 +0000 From: Sean Christopherson To: Anirudh Rayabharam Cc: Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Ilias Stamatis , Maxim Levitsky , mail@anirudhrb.com, kumarpraveen@linux.microsoft.com, wei.liu@kernel.org, robert.bradford@intel.com, liuwe@microsoft.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] KVM: nVMX: Don't expose TSC scaling to L1 when on Hyper-V Message-ID: References: <20220613161611.3567556-1-anrayabh@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220613161611.3567556-1-anrayabh@linux.microsoft.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, Jun 13, 2022, Anirudh Rayabharam wrote: > As per the comments in arch/x86/kvm/vmx/evmcs.h, TSC multiplier field is It's not just the comments, it's also the code. It would be helpful to call out in the changelog that KVM clears unsupported controls via evmcs_sanitize_exec_ctrls() when using eVMCS. > currently not supported in EVMCS. As a result, there is no TSC scaling > support when KVM is running on Hyper-V i.e. kvm_has_tsc_control is > false. > > However, in nested_vmx_setup_ctls_msrs(), TSC scaling is exposed to L1. > When L1 tries to launch an L2 guest, vmcs12 has TSC scaling enabled. > This propagates to vmcs02. But KVM doesn't set the TSC multiplier value > because kvm_has_tsc_control is false. Due to this, VM entry for L2 guest > fails. (VM entry fails if "use TSC scaling" is 1 and TSC multiplier is 0.) > > To fix, expose TSC scaling to L1 only if kvm_has_tsc_control. > > Fixes: d041b5ea93352 ("KVM: nVMX: Enable nested TSC scaling") > Signed-off-by: Anirudh Rayabharam > --- > arch/x86/kvm/vmx/nested.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c > index f5cb18e00e78..d773ddc6422b 100644 > --- a/arch/x86/kvm/vmx/nested.c > +++ b/arch/x86/kvm/vmx/nested.c > @@ -6656,6 +6656,9 @@ void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps) > msrs->secondary_ctls_low, > msrs->secondary_ctls_high); > > + if (!kvm_has_tsc_control) > + msrs->secondary_ctls_high &= ~SECONDARY_EXEC_TSC_SCALING; I would much rather we fix the root of the problem and not play whack-a-mole, e.g. all of the other controls that aren't supported by eVMCS have the same bug,. nested_vmx_setup_ctls_msrs() should use vmcs_config to get the base MSR values, not read the MSRs from hardware. And it's not just eVMCS, e.g. the manipulation of VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL for a CPU errata isn't handled either. > msrs->secondary_ctls_low = 0; > msrs->secondary_ctls_high &= > SECONDARY_EXEC_DESC | > @@ -6667,8 +6670,7 @@ void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps) > SECONDARY_EXEC_RDRAND_EXITING | > SECONDARY_EXEC_ENABLE_INVPCID | > SECONDARY_EXEC_RDSEED_EXITING | > - SECONDARY_EXEC_XSAVES | > - SECONDARY_EXEC_TSC_SCALING; > + SECONDARY_EXEC_XSAVES; > > /* > * We can emulate "VMCS shadowing," even if the hardware > -- > 2.34.1 >