Re: [PATCH v1] arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resets

[Matthias Kaehlcke <mka@chromium.org>]

On Tue, Jun 14, 2022 at 09:41:18PM +0530, Taniya Das wrote:
> The lpass audio supports TX/RX/WSA block resets. The LPASS PIL clock
> driver is not supported and mark it disabled. Also to keep consistency
> update lpasscore to lpass_core.

There is a driver for "qcom,sc7280-lpasscc", what does it mean that is
isn't supported?

IIUC one problem is that 'lpasscc@3000000' and 'lpass_aon / clock-controller@3380000'
have overlapping register ranges, so they can't be used together.

You could just say 'Disable the LPASS PIL clock by default, boards
can enable it if needed'.

> Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers")
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e66fc67de206..180cfd2765b9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2174,6 +2174,7 @@
>  			clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
>  			clock-names = "iface";
>  			#clock-cells = <1>;
> +			status = "disabled";
>  		};
> 
>  		lpass_audiocc: clock-controller@3300000 {
> @@ -2185,6 +2186,7 @@
>  			power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
>  			#clock-cells = <1>;
>  			#power-domain-cells = <1>;
> +			#reset-cells = <1>;
>  		};
> 
>  		lpass_aon: clock-controller@3380000 {
> @@ -2198,7 +2200,7 @@
>  			#power-domain-cells = <1>;
>  		};
> 
> -		lpasscore: clock-controller@3900000 {
> +		lpass_core: clock-controller@3900000 {
>  			compatible = "qcom,sc7280-lpasscorecc";
>  			reg = <0 0x03900000 0 0x50000>;
>  			clocks =  <&rpmhcc RPMH_CXO_CLK>;
> --
> 2.17.1
>