From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4ACDDC433EF for ; Thu, 23 Jun 2022 11:18:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6E0A310E7DA; Thu, 23 Jun 2022 11:18:57 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 63C4810E0F7; Thu, 23 Jun 2022 11:18:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655983136; x=1687519136; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=ZDmviisAQFt/A72ntxTrOHQF561xAWJ5eMxmpFohiy4=; b=YO6t7LWNyAcziP0pK0eqUpMiBlllpzZFP3qV3pzvFBst5N8jgqdiZDqi Z7dJbH0N7azDNnYeGaC0k2DhZEfH0eOtiLbHGXK+ZGTChAzo6dBIREzL2 FFKCxVZeVTETAVd3pijvHR7WXqHqDWfiHlAKodzpE+RiL1tFtesm8Pga4 3TEHqzDSADfxAi2kNW4F/RJLYuGMVBtsvm20OYtV9IU27Eu9GIbFwEwtz geKxhcvjdTMAk1UWFFMrJI+z0ukccasc1sG+7n4OrNtxZUax+RoTm1f3b ySqDUw7BITcOseA1K7CA3eKp73GiH1EEbsMPlcf3g0LWtGWhiYGhfnJkZ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10386"; a="279459552" X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="279459552" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:18:56 -0700 X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="644691087" Received: from hazegrou-mobl.ger.corp.intel.com (HELO intel.com) ([10.251.216.121]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:18:50 -0700 Date: Thu, 23 Jun 2022 13:18:47 +0200 From: Andi Shyti To: Mauro Carvalho Chehab Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Subject: Re: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Serialize TLB invalidates with GT resets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , dri-devel@lists.freedesktop.org, Chris Wilson , Matthew Auld , Dave Airlie , Thomas =?iso-8859-15?Q?Hellstr=F6m?= , intel-gfx@lists.freedesktop.org, Lucas De Marchi , Thomas Hellstrom , Rodrigo Vivi , mauro.chehab@linux.intel.com, =?utf-8?Q?Micha=C5=82?= Winiarski , linux-kernel@vger.kernel.org, stable@vger.kernel.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi Mauro, On Wed, Jun 15, 2022 at 04:27:40PM +0100, Mauro Carvalho Chehab wrote: > From: Chris Wilson > > Avoid trying to invalidate the TLB in the middle of performing an > engine reset, as this may result in the reset timing out. Currently, > the TLB invalidate is only serialised by its own mutex, forgoing the > uncore lock, but we can take the uncore->lock as well to serialise > the mmio access, thereby serialising with the GDRST. > > Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with > i915 selftest/hangcheck. > > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > > Reported-by: Mauro Carvalho Chehab > Tested-by: Mauro Carvalho Chehab > Reviewed-by: Mauro Carvalho Chehab > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > Cc: stable@vger.kernel.org > Acked-by: Thomas Hellström > Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Andi Shyti Thanks, Andi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01D0FC433EF for ; Thu, 23 Jun 2022 11:18:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230056AbiFWLS7 (ORCPT ); Thu, 23 Jun 2022 07:18:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229765AbiFWLS5 (ORCPT ); Thu, 23 Jun 2022 07:18:57 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F276D4BBA0; Thu, 23 Jun 2022 04:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655983137; x=1687519137; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=ZDmviisAQFt/A72ntxTrOHQF561xAWJ5eMxmpFohiy4=; b=Knkz5DmEYNKy7rBucfltf1wCQeZbmZDlm5A1yZf2G1qwGJvcSwr5dTjU 3XgrSCdTKAmfljqiWg2i9L1mCLlHFl4tV7Z3Mjt6mDBXjaRzDHHYqgYJ5 y//d80sRddUagmpAsiu2RLCEJqbYMDqX4OPRAvpPSYG/vd3swOAcMA9y7 ey5pV9rxCSVAlm5mtmc2Od2o5KulmgpdAsGuDYd7UJ/A+VcgU2M/BG6gz wMpOr2dEzTNEC+zy0cHV395IsvTylmMPx9muvjFbvu9lkfsX9/6iyEUG4 eJ7hAY2xS4UJo5W7sTs4lniyyK1P9FzJbUmQzaKnQVJIrmMC0SiJ1GcZd Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10386"; a="344682191" X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="344682191" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:18:56 -0700 X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="644691087" Received: from hazegrou-mobl.ger.corp.intel.com (HELO intel.com) ([10.251.216.121]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:18:50 -0700 Date: Thu, 23 Jun 2022 13:18:47 +0200 From: Andi Shyti To: Mauro Carvalho Chehab Cc: Chris Wilson , Fei Yang , =?utf-8?Q?Micha=C5=82?= Winiarski , Thomas Hellstrom , Thomas =?iso-8859-15?Q?Hellstr=F6m?= , Andi Shyti , Daniel Vetter , Daniele Ceraolo Spurio , Dave Airlie , David Airlie , Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Matt Roper , Matthew Auld , Rodrigo Vivi , Tvrtko Ursulin , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mauro.chehab@linux.intel.com, stable@vger.kernel.org Subject: Re: [PATCH 6/6] drm/i915/gt: Serialize TLB invalidates with GT resets Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Hi Mauro, On Wed, Jun 15, 2022 at 04:27:40PM +0100, Mauro Carvalho Chehab wrote: > From: Chris Wilson > > Avoid trying to invalidate the TLB in the middle of performing an > engine reset, as this may result in the reset timing out. Currently, > the TLB invalidate is only serialised by its own mutex, forgoing the > uncore lock, but we can take the uncore->lock as well to serialise > the mmio access, thereby serialising with the GDRST. > > Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with > i915 selftest/hangcheck. > > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > > Reported-by: Mauro Carvalho Chehab > Tested-by: Mauro Carvalho Chehab > Reviewed-by: Mauro Carvalho Chehab > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > Cc: stable@vger.kernel.org > Acked-by: Thomas Hellström > Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Andi Shyti Thanks, Andi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1808FC43334 for ; Thu, 23 Jun 2022 11:18:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CEF810E0F7; Thu, 23 Jun 2022 11:18:57 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 63C4810E0F7; Thu, 23 Jun 2022 11:18:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655983136; x=1687519136; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=ZDmviisAQFt/A72ntxTrOHQF561xAWJ5eMxmpFohiy4=; b=YO6t7LWNyAcziP0pK0eqUpMiBlllpzZFP3qV3pzvFBst5N8jgqdiZDqi Z7dJbH0N7azDNnYeGaC0k2DhZEfH0eOtiLbHGXK+ZGTChAzo6dBIREzL2 FFKCxVZeVTETAVd3pijvHR7WXqHqDWfiHlAKodzpE+RiL1tFtesm8Pga4 3TEHqzDSADfxAi2kNW4F/RJLYuGMVBtsvm20OYtV9IU27Eu9GIbFwEwtz geKxhcvjdTMAk1UWFFMrJI+z0ukccasc1sG+7n4OrNtxZUax+RoTm1f3b ySqDUw7BITcOseA1K7CA3eKp73GiH1EEbsMPlcf3g0LWtGWhiYGhfnJkZ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10386"; a="279459552" X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="279459552" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:18:56 -0700 X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="644691087" Received: from hazegrou-mobl.ger.corp.intel.com (HELO intel.com) ([10.251.216.121]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:18:50 -0700 Date: Thu, 23 Jun 2022 13:18:47 +0200 From: Andi Shyti To: Mauro Carvalho Chehab Subject: Re: [PATCH 6/6] drm/i915/gt: Serialize TLB invalidates with GT resets Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , Fei Yang , Chris Wilson , Matthew Auld , Andi Shyti , Dave Airlie , Thomas =?iso-8859-15?Q?Hellstr=F6m?= , intel-gfx@lists.freedesktop.org, Lucas De Marchi , Thomas Hellstrom , Rodrigo Vivi , Tvrtko Ursulin , mauro.chehab@linux.intel.com, =?utf-8?Q?Micha=C5=82?= Winiarski , linux-kernel@vger.kernel.org, stable@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Mauro, On Wed, Jun 15, 2022 at 04:27:40PM +0100, Mauro Carvalho Chehab wrote: > From: Chris Wilson > > Avoid trying to invalidate the TLB in the middle of performing an > engine reset, as this may result in the reset timing out. Currently, > the TLB invalidate is only serialised by its own mutex, forgoing the > uncore lock, but we can take the uncore->lock as well to serialise > the mmio access, thereby serialising with the GDRST. > > Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with > i915 selftest/hangcheck. > > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > > Reported-by: Mauro Carvalho Chehab > Tested-by: Mauro Carvalho Chehab > Reviewed-by: Mauro Carvalho Chehab > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > Cc: stable@vger.kernel.org > Acked-by: Thomas Hellström > Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Andi Shyti Thanks, Andi