From: Sean Christopherson <seanjc@google.com>
To: Chao Gao <chao.gao@intel.com>
Cc: Zeng Guang <guang.zeng@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>,
linux-kselftest@vger.kernel.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org,
Venkatesh Srinivas <venkateshs@chromium.org>
Subject: Re: [PATCH v2] KVM: selftest: Enhance handling WRMSR ICR register in x2APIC mode
Date: Thu, 23 Jun 2022 20:34:27 +0000 [thread overview]
Message-ID: <YrTOU1QHHpGpe0ym@google.com> (raw)
In-Reply-To: <20220623103314.GA14006@gao-cwp>
+Venkatesh
On Thu, Jun 23, 2022, Chao Gao wrote:
> On Thu, Jun 23, 2022 at 05:45:11PM +0800, Zeng Guang wrote:
> >Hardware would directly write x2APIC ICR register instead of software
> >emulation in some circumstances, e.g when Intel IPI virtualization is
> >enabled. This behavior requires normal reserved bits checking to ensure
> >them input as zero, otherwise it will cause #GP. So we need mask out
> >those reserved bits from the data written to vICR register.
>
> OK. One open is:
>
> Current KVM doesn't emulate this #GP. Is there any historical reason?
> if no, we will fix KVM and add some tests to verify this #GP is
> correctly emulated.
It's a bug. There are patches posted[*], but they need to be refreshed to fix a
rebase goof.
Venkatesh, are you planning on sending a v3 soonish?
[*] https://lore.kernel.org/all/20220525173933.1611076-1-venkateshs@chromium.org
next prev parent reply other threads:[~2022-06-23 20:34 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-23 9:45 [PATCH v2] KVM: selftest: Enhance handling WRMSR ICR register in x2APIC mode Zeng Guang
2022-06-23 10:33 ` Chao Gao
2022-06-23 20:34 ` Sean Christopherson [this message]
2022-06-24 2:55 ` Zeng Guang
2022-06-24 4:28 ` Zeng Guang
2022-06-24 5:48 ` Chao Gao
2022-06-24 8:05 ` Paolo Bonzini
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