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[86.27.177.88]) by smtp.gmail.com with ESMTPSA id x11-20020adff0cb000000b0021b92171d28sm13048073wro.54.2022.06.27.07.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 07:14:15 -0700 (PDT) Date: Mon, 27 Jun 2022 15:14:13 +0100 From: Lee Jones To: ChiaEn Wu Cc: jic23@kernel.org, lars@metafoo.de, matthias.bgg@gmail.com, Daniel Thompson , jingoohan1@gmail.com, pavel@ucw.cz, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-fbdev@vger.kernel.org, szunichen@gmail.com, ChiYuan Huang Subject: Re: [PATCH v2 08/15] mfd: mt6370: Add Mediatek MT6370 support Message-ID: References: <20220613111146.25221-1-peterwu.pub@gmail.com> <20220613111146.25221-9-peterwu.pub@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org On Sat, 18 Jun 2022, ChiaEn Wu wrote: > Hi Lee, > > Thanks for your helpful comments, we have some questions and replies below. > > Lee Jones 於 2022年6月16日 週四 清晨6:49寫道: > > > > > On Mon, 13 Jun 2022, ChiaEn Wu wrote: > > > > > From: ChiYuan Huang > > > > > > Add Mediatek MT6370 MFD support. > > > > > > Signed-off-by: ChiYuan Huang > > > --- > > > drivers/mfd/Kconfig | 13 ++ > > > drivers/mfd/Makefile | 1 + > > > drivers/mfd/mt6370.c | 349 +++++++++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 363 insertions(+) > > > create mode 100644 drivers/mfd/mt6370.c > > > > > > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > > > index 3b59456f5545..d9a7524a3e0e 100644 > > > --- a/drivers/mfd/Kconfig > > > +++ b/drivers/mfd/Kconfig > > > @@ -937,6 +937,19 @@ config MFD_MT6360 > > > PMIC part includes 2-channel BUCKs and 2-channel LDOs > > > LDO part includes 4-channel LDOs > > > > > > +config MFD_MT6370 > > > + tristate "Mediatek MT6370 SubPMIC" > > > + select MFD_CORE > > > + select REGMAP_I2C > > > + select REGMAP_IRQ > > > + depends on I2C > > > + help > > > + Say Y here to enable MT6370 SubPMIC functional support. > > > + It integrate single cell battery charger with adc monitoring, RGB > > > > s/integrates/consists of a/ > > > > "ADC" > > We will fine it in the next patch. > > > > > > + LEDs, dual channel flashlight, WLED backlight driver, display bias > > > > > + voltage supply, one general purpose LDO, and cc logic > > > + controller with USBPD commmunication capable. > > > > The last part makes no sense - "and is USBPD"? > > If we modify this help text to > "one general purpose LDO, and the USB Type-C & PD controller complies > with the latest USB Type-C and PD standards", > did these modifications meet your expectations? "one general purpose LDO and a USB Type-C & PD controller that complies with the latest USB Type-C and PD standards" Better? > > > config MFD_MT6397 > > > tristate "MediaTek MT6397 PMIC Support" > > > select MFD_CORE > > > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > > > index 858cacf659d6..62b27125420e 100644 > > > --- a/drivers/mfd/Makefile > > > +++ b/drivers/mfd/Makefile > > > @@ -242,6 +242,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o > > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o > > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o > > > obj-$(CONFIG_MFD_MT6360) += mt6360-core.o > > > +obj-$(CONFIG_MFD_MT6370) += mt6370.o > > > mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o > > > obj-$(CONFIG_MFD_MT6397) += mt6397.o > > > obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o > > > diff --git a/drivers/mfd/mt6370.c b/drivers/mfd/mt6370.c > > > new file mode 100644 > > > index 000000000000..6af9f73c9c0c > > > --- /dev/null > > > +++ b/drivers/mfd/mt6370.c > > > @@ -0,0 +1,349 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +enum { > > > + MT6370_USBC_I2C = 0, > > > + MT6370_PMU_I2C, > > > + MT6370_MAX_I2C > > > +}; > > > + > > > +#define MT6370_REG_DEV_INFO 0x100 > > > +#define MT6370_REG_CHG_IRQ1 0x1C0 > > > +#define MT6370_REG_CHG_MASK1 0x1E0 > > > + > > > +#define MT6370_VENID_MASK GENMASK(7, 4) > > > + > > > +#define MT6370_NUM_IRQREGS 16 > > > +#define MT6370_USBC_I2CADDR 0x4E > > > +#define MT6370_REG_ADDRLEN 2 > > > +#define MT6370_REG_MAXADDR 0x1FF > > > + > > > +/* IRQ definitions */ > > > +#define MT6370_IRQ_DIRCHGON 0 > > > +#define MT6370_IRQ_CHG_TREG 4 > > > +#define MT6370_IRQ_CHG_AICR 5 > > > +#define MT6370_IRQ_CHG_MIVR 6 > > > +#define MT6370_IRQ_PWR_RDY 7 > > > +#define MT6370_IRQ_FL_CHG_VINOVP 11 > > > +#define MT6370_IRQ_CHG_VSYSUV 12 > > > +#define MT6370_IRQ_CHG_VSYSOV 13 > > > +#define MT6370_IRQ_CHG_VBATOV 14 > > > +#define MT6370_IRQ_CHG_VINOVPCHG 15 > > > +#define MT6370_IRQ_TS_BAT_COLD 20 > > > +#define MT6370_IRQ_TS_BAT_COOL 21 > > > +#define MT6370_IRQ_TS_BAT_WARM 22 > > > +#define MT6370_IRQ_TS_BAT_HOT 23 > > > +#define MT6370_IRQ_TS_STATC 24 > > > +#define MT6370_IRQ_CHG_FAULT 25 > > > +#define MT6370_IRQ_CHG_STATC 26 > > > +#define MT6370_IRQ_CHG_TMR 27 > > > +#define MT6370_IRQ_CHG_BATABS 28 > > > +#define MT6370_IRQ_CHG_ADPBAD 29 > > > +#define MT6370_IRQ_CHG_RVP 30 > > > +#define MT6370_IRQ_TSHUTDOWN 31 > > > +#define MT6370_IRQ_CHG_IINMEAS 32 > > > +#define MT6370_IRQ_CHG_ICCMEAS 33 > > > +#define MT6370_IRQ_CHGDET_DONE 34 > > > +#define MT6370_IRQ_WDTMR 35 > > > +#define MT6370_IRQ_SSFINISH 36 > > > +#define MT6370_IRQ_CHG_RECHG 37 > > > +#define MT6370_IRQ_CHG_TERM 38 > > > +#define MT6370_IRQ_CHG_IEOC 39 > > > +#define MT6370_IRQ_ADC_DONE 40 > > > +#define MT6370_IRQ_PUMPX_DONE 41 > > > +#define MT6370_IRQ_BST_BATUV 45 > > > +#define MT6370_IRQ_BST_MIDOV 46 > > > +#define MT6370_IRQ_BST_OLP 47 > > > +#define MT6370_IRQ_ATTACH 48 > > > +#define MT6370_IRQ_DETACH 49 > > > +#define MT6370_IRQ_HVDCP_STPDONE 51 > > > +#define MT6370_IRQ_HVDCP_VBUSDET_DONE 52 > > > +#define MT6370_IRQ_HVDCP_DET 53 > > > +#define MT6370_IRQ_CHGDET 54 > > > +#define MT6370_IRQ_DCDT 55 > > > +#define MT6370_IRQ_DIRCHG_VGOK 59 > > > +#define MT6370_IRQ_DIRCHG_WDTMR 60 > > > +#define MT6370_IRQ_DIRCHG_UC 61 > > > +#define MT6370_IRQ_DIRCHG_OC 62 > > > +#define MT6370_IRQ_DIRCHG_OV 63 > > > +#define MT6370_IRQ_OVPCTRL_SWON 67 > > > +#define MT6370_IRQ_OVPCTRL_UVP_D 68 > > > +#define MT6370_IRQ_OVPCTRL_UVP 69 > > > +#define MT6370_IRQ_OVPCTRL_OVP_D 70 > > > +#define MT6370_IRQ_OVPCTRL_OVP 71 > > > +#define MT6370_IRQ_FLED_STRBPIN 72 > > > +#define MT6370_IRQ_FLED_TORPIN 73 > > > +#define MT6370_IRQ_FLED_TX 74 > > > +#define MT6370_IRQ_FLED_LVF 75 > > > +#define MT6370_IRQ_FLED2_SHORT 78 > > > +#define MT6370_IRQ_FLED1_SHORT 79 > > > +#define MT6370_IRQ_FLED2_STRB 80 > > > +#define MT6370_IRQ_FLED1_STRB 81 > > > +#define mT6370_IRQ_FLED2_STRB_TO 82 > > > +#define MT6370_IRQ_FLED1_STRB_TO 83 > > > +#define MT6370_IRQ_FLED2_TOR 84 > > > +#define MT6370_IRQ_FLED1_TOR 85 > > > +#define MT6370_IRQ_OTP 93 > > > +#define MT6370_IRQ_VDDA_OVP 94 > > > +#define MT6370_IRQ_VDDA_UV 95 > > > +#define MT6370_IRQ_LDO_OC 103 > > > +#define MT6370_IRQ_BLED_OCP 118 > > > +#define MT6370_IRQ_BLED_OVP 119 > > > +#define MT6370_IRQ_DSV_VNEG_OCP 123 > > > +#define MT6370_IRQ_DSV_VPOS_OCP 124 > > > +#define MT6370_IRQ_DSV_BST_OCP 125 > > > +#define MT6370_IRQ_DSV_VNEG_SCP 126 > > > +#define MT6370_IRQ_DSV_VPOS_SCP 127 > > > + > > > +struct mt6370_info { > > > + struct i2c_client *i2c[MT6370_MAX_I2C]; > > > + struct device *dev; > > > + struct regmap *regmap; > > > + struct regmap_irq_chip_data *irq_data; > > > +}; > > > > Can we shove all of the above into a header file? > > Well... In Patch v1, we put these "#define IRQ" into > "include/dt-bindings/mfd/mediatek,mt6370.h". > But the reviewer of DT files hoped us to remove this header file, we > put these "#define IRQ" in this .c file. > Shall we leave them here or put them into the header file in > "driver/power/supply/mt6370-charger.h"? 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[86.27.177.88]) by smtp.gmail.com with ESMTPSA id x11-20020adff0cb000000b0021b92171d28sm13048073wro.54.2022.06.27.07.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 07:14:15 -0700 (PDT) Date: Mon, 27 Jun 2022 15:14:13 +0100 From: Lee Jones To: ChiaEn Wu Cc: jic23@kernel.org, lars@metafoo.de, matthias.bgg@gmail.com, Daniel Thompson , jingoohan1@gmail.com, pavel@ucw.cz, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-fbdev@vger.kernel.org, szunichen@gmail.com, ChiYuan Huang Subject: Re: [PATCH v2 08/15] mfd: mt6370: Add Mediatek MT6370 support Message-ID: References: <20220613111146.25221-1-peterwu.pub@gmail.com> <20220613111146.25221-9-peterwu.pub@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_071420_430228_50EE85DA X-CRM114-Status: GOOD ( 31.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gU2F0LCAxOCBKdW4gMjAyMiwgQ2hpYUVuIFd1IHdyb3RlOgoKPiBIaSBMZWUsCj4gCj4gVGhh bmtzIGZvciB5b3VyIGhlbHBmdWwgY29tbWVudHMsIHdlIGhhdmUgc29tZSBxdWVzdGlvbnMgYW5k IHJlcGxpZXMgYmVsb3cuCj4gCj4gTGVlIEpvbmVzIDxsZWUuam9uZXNAbGluYXJvLm9yZz4g5pa8 IDIwMjLlubQ25pyIMTbml6Ug6YCx5ZubIOa4heaZqDY6NDnlr6vpgZPvvJoKPiAKPiA+Cj4gPiBP biBNb24sIDEzIEp1biAyMDIyLCBDaGlhRW4gV3Ugd3JvdGU6Cj4gPgo+ID4gPiBGcm9tOiBDaGlZ dWFuIEh1YW5nIDxjeV9odWFuZ0ByaWNodGVrLmNvbT4KPiA+ID4KPiA+ID4gQWRkIE1lZGlhdGVr IE1UNjM3MCBNRkQgc3VwcG9ydC4KPiA+ID4KPiA+ID4gU2lnbmVkLW9mZi1ieTogQ2hpWXVhbiBI dWFuZyA8Y3lfaHVhbmdAcmljaHRlay5jb20+Cj4gPiA+IC0tLQo+ID4gPiAgZHJpdmVycy9tZmQv S2NvbmZpZyAgfCAgMTMgKysKPiA+ID4gIGRyaXZlcnMvbWZkL01ha2VmaWxlIHwgICAxICsKPiA+ ID4gIGRyaXZlcnMvbWZkL210NjM3MC5jIHwgMzQ5ICsrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysKPiA+ID4gIDMgZmlsZXMgY2hhbmdlZCwgMzYzIGluc2VydGlvbnMo KykKPiA+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL21mZC9tdDYzNzAuYwo+ID4gPgo+ ID4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tZmQvS2NvbmZpZyBiL2RyaXZlcnMvbWZkL0tjb25m aWcKPiA+ID4gaW5kZXggM2I1OTQ1NmY1NTQ1Li5kOWE3NTI0YTNlMGUgMTAwNjQ0Cj4gPiA+IC0t LSBhL2RyaXZlcnMvbWZkL0tjb25maWcKPiA+ID4gKysrIGIvZHJpdmVycy9tZmQvS2NvbmZpZwo+ ID4gPiBAQCAtOTM3LDYgKzkzNywxOSBAQCBjb25maWcgTUZEX01UNjM2MAo+ID4gPiAgICAgICAg IFBNSUMgcGFydCBpbmNsdWRlcyAyLWNoYW5uZWwgQlVDS3MgYW5kIDItY2hhbm5lbCBMRE9zCj4g PiA+ICAgICAgICAgTERPIHBhcnQgaW5jbHVkZXMgNC1jaGFubmVsIExET3MKPiA+ID4KPiA+ID4g K2NvbmZpZyBNRkRfTVQ2MzcwCj4gPiA+ICsgICAgIHRyaXN0YXRlICJNZWRpYXRlayBNVDYzNzAg U3ViUE1JQyIKPiA+ID4gKyAgICAgc2VsZWN0IE1GRF9DT1JFCj4gPiA+ICsgICAgIHNlbGVjdCBS RUdNQVBfSTJDCj4gPiA+ICsgICAgIHNlbGVjdCBSRUdNQVBfSVJRCj4gPiA+ICsgICAgIGRlcGVu ZHMgb24gSTJDCj4gPiA+ICsgICAgIGhlbHAKPiA+ID4gKyAgICAgICBTYXkgWSBoZXJlIHRvIGVu YWJsZSBNVDYzNzAgU3ViUE1JQyBmdW5jdGlvbmFsIHN1cHBvcnQuCj4gPiA+ICsgICAgICAgSXQg aW50ZWdyYXRlIHNpbmdsZSBjZWxsIGJhdHRlcnkgY2hhcmdlciB3aXRoIGFkYyBtb25pdG9yaW5n LCBSR0IKPiA+Cj4gPiBzL2ludGVncmF0ZXMvY29uc2lzdHMgb2YgYS8KPiA+Cj4gPiAiQURDIgo+ IAo+IFdlIHdpbGwgZmluZSBpdCBpbiB0aGUgbmV4dCBwYXRjaC4KPiAKPiA+Cj4gPiA+ICsgICAg ICAgTEVEcywgZHVhbCBjaGFubmVsIGZsYXNobGlnaHQsIFdMRUQgYmFja2xpZ2h0IGRyaXZlciwg ZGlzcGxheSBiaWFzCj4gPgo+ID4gPiArICAgICAgIHZvbHRhZ2Ugc3VwcGx5LCBvbmUgZ2VuZXJh bCBwdXJwb3NlIExETywgYW5kIGNjIGxvZ2ljCj4gPiA+ICsgICAgICAgY29udHJvbGxlciB3aXRo IFVTQlBEIGNvbW1tdW5pY2F0aW9uIGNhcGFibGUuCj4gPgo+ID4gVGhlIGxhc3QgcGFydCBtYWtl cyBubyBzZW5zZSAtICJhbmQgaXMgVVNCUEQiPwo+IAo+IElmIHdlIG1vZGlmeSB0aGlzIGhlbHAg dGV4dCB0bwo+ICJvbmUgZ2VuZXJhbCBwdXJwb3NlIExETywgYW5kIHRoZSBVU0IgVHlwZS1DICYg UEQgY29udHJvbGxlciBjb21wbGllcwo+IHdpdGggdGhlIGxhdGVzdCBVU0IgVHlwZS1DIGFuZCBQ RCBzdGFuZGFyZHMiLAo+IGRpZCB0aGVzZSBtb2RpZmljYXRpb25zIG1lZXQgeW91ciBleHBlY3Rh dGlvbnM/Cgoib25lIGdlbmVyYWwgcHVycG9zZSBMRE8gYW5kIGEgVVNCIFR5cGUtQyAmIFBEIGNv bnRyb2xsZXIgdGhhdApjb21wbGllcyB3aXRoIHRoZSBsYXRlc3QgVVNCIFR5cGUtQyBhbmQgUEQg c3RhbmRhcmRzIgoKQmV0dGVyPwoKPiA+ID4gIGNvbmZpZyBNRkRfTVQ2Mzk3Cj4gPiA+ICAgICAg IHRyaXN0YXRlICJNZWRpYVRlayBNVDYzOTcgUE1JQyBTdXBwb3J0Igo+ID4gPiAgICAgICBzZWxl Y3QgTUZEX0NPUkUKPiA+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbWZkL01ha2VmaWxlIGIvZHJp dmVycy9tZmQvTWFrZWZpbGUKPiA+ID4gaW5kZXggODU4Y2FjZjY1OWQ2Li42MmIyNzEyNTQyMGUg MTAwNjQ0Cj4gPiA+IC0tLSBhL2RyaXZlcnMvbWZkL01ha2VmaWxlCj4gPiA+ICsrKyBiL2RyaXZl cnMvbWZkL01ha2VmaWxlCj4gPiA+IEBAIC0yNDIsNiArMjQyLDcgQEAgb2JqLSQoQ09ORklHX0lO VEVMX1NPQ19QTUlDX0JYVFdDKSAgICAgICAgKz0gaW50ZWxfc29jX3BtaWNfYnh0d2Mubwo+ID4g PiAgb2JqLSQoQ09ORklHX0lOVEVMX1NPQ19QTUlDX0NIVFdDKSAgICs9IGludGVsX3NvY19wbWlj X2NodHdjLm8KPiA+ID4gIG9iai0kKENPTkZJR19JTlRFTF9TT0NfUE1JQ19DSFREQ19USSkgICAg ICAgICs9IGludGVsX3NvY19wbWljX2NodGRjX3RpLm8KPiA+ID4gIG9iai0kKENPTkZJR19NRkRf TVQ2MzYwKSAgICAgKz0gbXQ2MzYwLWNvcmUubwo+ID4gPiArb2JqLSQoQ09ORklHX01GRF9NVDYz NzApICAgICArPSBtdDYzNzAubwo+ID4gPiAgbXQ2Mzk3LW9ianMgICAgICAgICAgICAgICAgICA6 PSBtdDYzOTctY29yZS5vIG10NjM5Ny1pcnEubyBtdDYzNTgtaXJxLm8KPiA+ID4gIG9iai0kKENP TkZJR19NRkRfTVQ2Mzk3KSAgICAgKz0gbXQ2Mzk3Lm8KPiA+ID4gIG9iai0kKENPTkZJR19JTlRF TF9TT0NfUE1JQ19NUkZMRCkgICArPSBpbnRlbF9zb2NfcG1pY19tcmZsZC5vCj4gPiA+IGRpZmYg LS1naXQgYS9kcml2ZXJzL21mZC9tdDYzNzAuYyBiL2RyaXZlcnMvbWZkL210NjM3MC5jCj4gPiA+ IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gPiA+IGluZGV4IDAwMDAwMDAwMDAwMC4uNmFmOWY3M2M5 YzBjCj4gPiA+IC0tLSAvZGV2L251bGwKPiA+ID4gKysrIGIvZHJpdmVycy9tZmQvbXQ2MzcwLmMK PiA+ID4gQEAgLTAsMCArMSwzNDkgQEAKPiA+ID4gKy8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVy OiBHUEwtMi4wCj4gPiA+ICsKPiA+ID4gKyNpbmNsdWRlIDxsaW51eC9iaXRzLmg+Cj4gPiA+ICsj aW5jbHVkZSA8bGludXgvaTJjLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvaW50ZXJydXB0Lmg+ Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgva2VybmVsLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgv bWZkL2NvcmUuaD4KPiA+ID4gKyNpbmNsdWRlIDxsaW51eC9tb2R1bGUuaD4KPiA+ID4gKyNpbmNs dWRlIDxsaW51eC9yZWdtYXAuaD4KPiA+ID4gKwo+ID4gPiArZW51bSB7Cj4gPiA+ICsgICAgIE1U NjM3MF9VU0JDX0kyQyA9IDAsCj4gPiA+ICsgICAgIE1UNjM3MF9QTVVfSTJDLAo+ID4gPiArICAg ICBNVDYzNzBfTUFYX0kyQwo+ID4gPiArfTsKPiA+ID4gKwo+ID4gPiArI2RlZmluZSBNVDYzNzBf UkVHX0RFVl9JTkZPICAweDEwMAo+ID4gPiArI2RlZmluZSBNVDYzNzBfUkVHX0NIR19JUlExICAw eDFDMAo+ID4gPiArI2RlZmluZSBNVDYzNzBfUkVHX0NIR19NQVNLMSAweDFFMAo+ID4gPiArCj4g PiA+ICsjZGVmaW5lIE1UNjM3MF9WRU5JRF9NQVNLICAgIEdFTk1BU0soNywgNCkKPiA+ID4gKwo+ ID4gPiArI2RlZmluZSBNVDYzNzBfTlVNX0lSUVJFR1MgICAxNgo+ID4gPiArI2RlZmluZSBNVDYz NzBfVVNCQ19JMkNBRERSICAweDRFCj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9SRUdfQUREUkxFTiAg IDIKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX1JFR19NQVhBRERSICAgMHgxRkYKPiA+ID4gKwo+ID4g PiArLyogSVJRIGRlZmluaXRpb25zICovCj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfRElSQ0hH T04gICAgICAgICAgMAo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0NIR19UUkVHICAgICAgICAg IDQKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9DSEdfQUlDUiAgICAgICAgICA1Cj4gPiA+ICsj ZGVmaW5lIE1UNjM3MF9JUlFfQ0hHX01JVlIgICAgICAgICAgNgo+ID4gPiArI2RlZmluZSBNVDYz NzBfSVJRX1BXUl9SRFkgICAgICAgICAgIDcKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9GTF9D SEdfVklOT1ZQICAgICAxMQo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0NIR19WU1lTVVYgICAg ICAgICAgICAgICAgMTIKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9DSEdfVlNZU09WICAgICAg ICAgICAgICAgIDEzCj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfQ0hHX1ZCQVRPViAgICAgICAg ICAgICAgICAxNAo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0NIR19WSU5PVlBDSEcgICAgIDE1 Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfVFNfQkFUX0NPTEQgICAgICAgICAgICAgICAyMAo+ ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX1RTX0JBVF9DT09MICAgICAgICAgICAgICAgMjEKPiA+ ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9UU19CQVRfV0FSTSAgICAgICAgICAgICAgIDIyCj4gPiA+ ICsjZGVmaW5lIE1UNjM3MF9JUlFfVFNfQkFUX0hPVCAgICAgICAgICAgICAgICAyMwo+ID4gPiAr I2RlZmluZSBNVDYzNzBfSVJRX1RTX1NUQVRDICAgICAgICAgIDI0Cj4gPiA+ICsjZGVmaW5lIE1U NjM3MF9JUlFfQ0hHX0ZBVUxUICAgICAgICAgMjUKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9D SEdfU1RBVEMgICAgICAgICAyNgo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0NIR19UTVIgICAg ICAgICAgIDI3Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfQ0hHX0JBVEFCUyAgICAgICAgICAg ICAgICAyOAo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0NIR19BRFBCQUQgICAgICAgICAgICAg ICAgMjkKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9DSEdfUlZQICAgICAgICAgICAzMAo+ID4g PiArI2RlZmluZSBNVDYzNzBfSVJRX1RTSFVURE9XTiAgICAgICAgIDMxCj4gPiA+ICsjZGVmaW5l IE1UNjM3MF9JUlFfQ0hHX0lJTk1FQVMgICAgICAgICAgICAgICAzMgo+ID4gPiArI2RlZmluZSBN VDYzNzBfSVJRX0NIR19JQ0NNRUFTICAgICAgICAgICAgICAgMzMKPiA+ID4gKyNkZWZpbmUgTVQ2 MzcwX0lSUV9DSEdERVRfRE9ORSAgICAgICAgICAgICAgIDM0Cj4gPiA+ICsjZGVmaW5lIE1UNjM3 MF9JUlFfV0RUTVIgICAgICAgICAgICAgMzUKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9TU0ZJ TklTSCAgICAgICAgICAzNgo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0NIR19SRUNIRyAgICAg ICAgIDM3Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfQ0hHX1RFUk0gICAgICAgICAgMzgKPiA+ ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9DSEdfSUVPQyAgICAgICAgICAzOQo+ID4gPiArI2RlZmlu ZSBNVDYzNzBfSVJRX0FEQ19ET05FICAgICAgICAgIDQwCj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9J UlFfUFVNUFhfRE9ORSAgICAgICAgICAgICAgICA0MQo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJR X0JTVF9CQVRVViAgICAgICAgIDQ1Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfQlNUX01JRE9W ICAgICAgICAgNDYKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9CU1RfT0xQICAgICAgICAgICA0 Nwo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0FUVEFDSCAgICAgICAgICAgIDQ4Cj4gPiA+ICsj ZGVmaW5lIE1UNjM3MF9JUlFfREVUQUNIICAgICAgICAgICAgNDkKPiA+ID4gKyNkZWZpbmUgTVQ2 MzcwX0lSUV9IVkRDUF9TVFBET05FICAgICA1MQo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0hW RENQX1ZCVVNERVRfRE9ORSAgICAgICAgNTIKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9IVkRD UF9ERVQgICAgICAgICA1Mwo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0NIR0RFVCAgICAgICAg ICAgIDU0Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfRENEVCAgICAgICAgICAgICAgICAgICAg ICA1NQo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0RJUkNIR19WR09LICAgICAgICAgICAgICAg NTkKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9ESVJDSEdfV0RUTVIgICAgICAgICAgICAgIDYw Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfRElSQ0hHX1VDICAgICAgICAgNjEKPiA+ID4gKyNk ZWZpbmUgTVQ2MzcwX0lSUV9ESVJDSEdfT0MgICAgICAgICA2Mgo+ID4gPiArI2RlZmluZSBNVDYz NzBfSVJRX0RJUkNIR19PViAgICAgICAgIDYzCj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfT1ZQ Q1RSTF9TV09OICAgICAgICAgICAgICA2Nwo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX09WUENU UkxfVVZQX0QgICAgIDY4Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfT1ZQQ1RSTF9VVlAgICAg ICAgICAgICAgICA2OQo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX09WUENUUkxfT1ZQX0QgICAg IDcwCj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfT1ZQQ1RSTF9PVlAgICAgICAgICAgICAgICA3 MQo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0ZMRURfU1RSQlBJTiAgICAgICAgICAgICAgNzIK PiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9GTEVEX1RPUlBJTiAgICAgICAgICAgICAgIDczCj4g PiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfRkxFRF9UWCAgICAgICAgICAgNzQKPiA+ID4gKyNkZWZp bmUgTVQ2MzcwX0lSUV9GTEVEX0xWRiAgICAgICAgICA3NQo+ID4gPiArI2RlZmluZSBNVDYzNzBf SVJRX0ZMRUQyX1NIT1JUICAgICAgICAgICAgICAgNzgKPiA+ID4gKyNkZWZpbmUgTVQ2MzcwX0lS UV9GTEVEMV9TSE9SVCAgICAgICAgICAgICAgIDc5Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFf RkxFRDJfU1RSQiAgICAgICAgICAgICAgICA4MAo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0ZM RUQxX1NUUkIgICAgICAgICAgICAgICAgODEKPiA+ID4gKyNkZWZpbmUgbVQ2MzcwX0lSUV9GTEVE Ml9TVFJCX1RPICAgICA4Mgo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJRX0ZMRUQxX1NUUkJfVE8g ICAgIDgzCj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfRkxFRDJfVE9SICAgICAgICAgODQKPiA+ ID4gKyNkZWZpbmUgTVQ2MzcwX0lSUV9GTEVEMV9UT1IgICAgICAgICA4NQo+ID4gPiArI2RlZmlu ZSBNVDYzNzBfSVJRX09UUCAgICAgICAgICAgICAgICAgICAgICAgOTMKPiA+ID4gKyNkZWZpbmUg TVQ2MzcwX0lSUV9WRERBX09WUCAgICAgICAgICA5NAo+ID4gPiArI2RlZmluZSBNVDYzNzBfSVJR X1ZEREFfVVYgICAgICAgICAgIDk1Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfTERPX09DICAg ICAgICAgICAgMTAzCj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfQkxFRF9PQ1AgICAgICAgICAg MTE4Cj4gPiA+ICsjZGVmaW5lIE1UNjM3MF9JUlFfQkxFRF9PVlAgICAgICAgICAgMTE5Cj4gPiA+ ICsjZGVmaW5lIE1UNjM3MF9JUlFfRFNWX1ZORUdfT0NQICAgICAgICAgICAgICAxMjMKPiA+ID4g KyNkZWZpbmUgTVQ2MzcwX0lSUV9EU1ZfVlBPU19PQ1AgICAgICAgICAgICAgIDEyNAo+ID4gPiAr I2RlZmluZSBNVDYzNzBfSVJRX0RTVl9CU1RfT0NQICAgICAgICAgICAgICAgMTI1Cj4gPiA+ICsj ZGVmaW5lIE1UNjM3MF9JUlFfRFNWX1ZORUdfU0NQICAgICAgICAgICAgICAxMjYKPiA+ID4gKyNk ZWZpbmUgTVQ2MzcwX0lSUV9EU1ZfVlBPU19TQ1AgICAgICAgICAgICAgIDEyNwo+ID4gPiArCj4g PiA+ICtzdHJ1Y3QgbXQ2MzcwX2luZm8gewo+ID4gPiArICAgICBzdHJ1Y3QgaTJjX2NsaWVudCAq aTJjW01UNjM3MF9NQVhfSTJDXTsKPiA+ID4gKyAgICAgc3RydWN0IGRldmljZSAqZGV2Owo+ID4g PiArICAgICBzdHJ1Y3QgcmVnbWFwICpyZWdtYXA7Cj4gPiA+ICsgICAgIHN0cnVjdCByZWdtYXBf aXJxX2NoaXBfZGF0YSAqaXJxX2RhdGE7Cj4gPiA+ICt9Owo+ID4KPiA+IENhbiB3ZSBzaG92ZSBh bGwgb2YgdGhlIGFib3ZlIGludG8gYSBoZWFkZXIgZmlsZT8KPiAKPiBXZWxsLi4uIEluIFBhdGNo IHYxLCB3ZSBwdXQgdGhlc2UgIiNkZWZpbmUgSVJRIiBpbnRvCj4gImluY2x1ZGUvZHQtYmluZGlu Z3MvbWZkL21lZGlhdGVrLG10NjM3MC5oIi4KPiBCdXQgdGhlIHJldmlld2VyIG9mIERUIGZpbGVz IGhvcGVkIHVzIHRvIHJlbW92ZSB0aGlzIGhlYWRlciBmaWxlLCB3ZQo+IHB1dCB0aGVzZSAiI2Rl ZmluZSBJUlEiIGluIHRoaXMgLmMgZmlsZS4KPiBTaGFsbCB3ZSBsZWF2ZSB0aGVtIGhlcmUgb3Ig cHV0IHRoZW0gaW50byB0aGUgaGVhZGVyIGZpbGUgaW4KPiAiZHJpdmVyL3Bvd2VyL3N1cHBseS9t dDYzNzAtY2hhcmdlci5oIj8KCldoZXJlIGFyZSB0aGV5IHVzZWQ/CgotLSAKTGVlIEpvbmVzIFvm nY7nkLzmlq9dClByaW5jaXBhbCBUZWNobmljYWwgTGVhZCAtIERldmVsb3BlciBTZXJ2aWNlcwpM aW5hcm8ub3JnIOKUgiBPcGVuIHNvdXJjZSBzb2Z0d2FyZSBmb3IgQXJtIFNvQ3MKRm9sbG93IExp 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[86.27.177.88]) by smtp.gmail.com with ESMTPSA id x11-20020adff0cb000000b0021b92171d28sm13048073wro.54.2022.06.27.07.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 07:14:15 -0700 (PDT) Date: Mon, 27 Jun 2022 15:14:13 +0100 From: Lee Jones To: ChiaEn Wu Subject: Re: [PATCH v2 08/15] mfd: mt6370: Add Mediatek MT6370 support Message-ID: References: <20220613111146.25221-1-peterwu.pub@gmail.com> <20220613111146.25221-9-peterwu.pub@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Daniel Thompson , krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-iio@vger.kernel.org, jingoohan1@gmail.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-fbdev@vger.kernel.org, ChiYuan Huang , szunichen@gmail.com, robh+dt@kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, pavel@ucw.cz, matthias.bgg@gmail.com, linux-leds@vger.kernel.org, jic23@kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Sat, 18 Jun 2022, ChiaEn Wu wrote: > Hi Lee, > > Thanks for your helpful comments, we have some questions and replies below. > > Lee Jones 於 2022年6月16日 週四 清晨6:49寫道: > > > > > On Mon, 13 Jun 2022, ChiaEn Wu wrote: > > > > > From: ChiYuan Huang > > > > > > Add Mediatek MT6370 MFD support. > > > > > > Signed-off-by: ChiYuan Huang > > > --- > > > drivers/mfd/Kconfig | 13 ++ > > > drivers/mfd/Makefile | 1 + > > > drivers/mfd/mt6370.c | 349 +++++++++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 363 insertions(+) > > > create mode 100644 drivers/mfd/mt6370.c > > > > > > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > > > index 3b59456f5545..d9a7524a3e0e 100644 > > > --- a/drivers/mfd/Kconfig > > > +++ b/drivers/mfd/Kconfig > > > @@ -937,6 +937,19 @@ config MFD_MT6360 > > > PMIC part includes 2-channel BUCKs and 2-channel LDOs > > > LDO part includes 4-channel LDOs > > > > > > +config MFD_MT6370 > > > + tristate "Mediatek MT6370 SubPMIC" > > > + select MFD_CORE > > > + select REGMAP_I2C > > > + select REGMAP_IRQ > > > + depends on I2C > > > + help > > > + Say Y here to enable MT6370 SubPMIC functional support. > > > + It integrate single cell battery charger with adc monitoring, RGB > > > > s/integrates/consists of a/ > > > > "ADC" > > We will fine it in the next patch. > > > > > > + LEDs, dual channel flashlight, WLED backlight driver, display bias > > > > > + voltage supply, one general purpose LDO, and cc logic > > > + controller with USBPD commmunication capable. > > > > The last part makes no sense - "and is USBPD"? > > If we modify this help text to > "one general purpose LDO, and the USB Type-C & PD controller complies > with the latest USB Type-C and PD standards", > did these modifications meet your expectations? "one general purpose LDO and a USB Type-C & PD controller that complies with the latest USB Type-C and PD standards" Better? > > > config MFD_MT6397 > > > tristate "MediaTek MT6397 PMIC Support" > > > select MFD_CORE > > > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > > > index 858cacf659d6..62b27125420e 100644 > > > --- a/drivers/mfd/Makefile > > > +++ b/drivers/mfd/Makefile > > > @@ -242,6 +242,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o > > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o > > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o > > > obj-$(CONFIG_MFD_MT6360) += mt6360-core.o > > > +obj-$(CONFIG_MFD_MT6370) += mt6370.o > > > mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o > > > obj-$(CONFIG_MFD_MT6397) += mt6397.o > > > obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o > > > diff --git a/drivers/mfd/mt6370.c b/drivers/mfd/mt6370.c > > > new file mode 100644 > > > index 000000000000..6af9f73c9c0c > > > --- /dev/null > > > +++ b/drivers/mfd/mt6370.c > > > @@ -0,0 +1,349 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +enum { > > > + MT6370_USBC_I2C = 0, > > > + MT6370_PMU_I2C, > > > + MT6370_MAX_I2C > > > +}; > > > + > > > +#define MT6370_REG_DEV_INFO 0x100 > > > +#define MT6370_REG_CHG_IRQ1 0x1C0 > > > +#define MT6370_REG_CHG_MASK1 0x1E0 > > > + > > > +#define MT6370_VENID_MASK GENMASK(7, 4) > > > + > > > +#define MT6370_NUM_IRQREGS 16 > > > +#define MT6370_USBC_I2CADDR 0x4E > > > +#define MT6370_REG_ADDRLEN 2 > > > +#define MT6370_REG_MAXADDR 0x1FF > > > + > > > +/* IRQ definitions */ > > > +#define MT6370_IRQ_DIRCHGON 0 > > > +#define MT6370_IRQ_CHG_TREG 4 > > > +#define MT6370_IRQ_CHG_AICR 5 > > > +#define MT6370_IRQ_CHG_MIVR 6 > > > +#define MT6370_IRQ_PWR_RDY 7 > > > +#define MT6370_IRQ_FL_CHG_VINOVP 11 > > > +#define MT6370_IRQ_CHG_VSYSUV 12 > > > +#define MT6370_IRQ_CHG_VSYSOV 13 > > > +#define MT6370_IRQ_CHG_VBATOV 14 > > > +#define MT6370_IRQ_CHG_VINOVPCHG 15 > > > +#define MT6370_IRQ_TS_BAT_COLD 20 > > > +#define MT6370_IRQ_TS_BAT_COOL 21 > > > +#define MT6370_IRQ_TS_BAT_WARM 22 > > > +#define MT6370_IRQ_TS_BAT_HOT 23 > > > +#define MT6370_IRQ_TS_STATC 24 > > > +#define MT6370_IRQ_CHG_FAULT 25 > > > +#define MT6370_IRQ_CHG_STATC 26 > > > +#define MT6370_IRQ_CHG_TMR 27 > > > +#define MT6370_IRQ_CHG_BATABS 28 > > > +#define MT6370_IRQ_CHG_ADPBAD 29 > > > +#define MT6370_IRQ_CHG_RVP 30 > > > +#define MT6370_IRQ_TSHUTDOWN 31 > > > +#define MT6370_IRQ_CHG_IINMEAS 32 > > > +#define MT6370_IRQ_CHG_ICCMEAS 33 > > > +#define MT6370_IRQ_CHGDET_DONE 34 > > > +#define MT6370_IRQ_WDTMR 35 > > > +#define MT6370_IRQ_SSFINISH 36 > > > +#define MT6370_IRQ_CHG_RECHG 37 > > > +#define MT6370_IRQ_CHG_TERM 38 > > > +#define MT6370_IRQ_CHG_IEOC 39 > > > +#define MT6370_IRQ_ADC_DONE 40 > > > +#define MT6370_IRQ_PUMPX_DONE 41 > > > +#define MT6370_IRQ_BST_BATUV 45 > > > +#define MT6370_IRQ_BST_MIDOV 46 > > > +#define MT6370_IRQ_BST_OLP 47 > > > +#define MT6370_IRQ_ATTACH 48 > > > +#define MT6370_IRQ_DETACH 49 > > > +#define MT6370_IRQ_HVDCP_STPDONE 51 > > > +#define MT6370_IRQ_HVDCP_VBUSDET_DONE 52 > > > +#define MT6370_IRQ_HVDCP_DET 53 > > > +#define MT6370_IRQ_CHGDET 54 > > > +#define MT6370_IRQ_DCDT 55 > > > +#define MT6370_IRQ_DIRCHG_VGOK 59 > > > +#define MT6370_IRQ_DIRCHG_WDTMR 60 > > > +#define MT6370_IRQ_DIRCHG_UC 61 > > > +#define MT6370_IRQ_DIRCHG_OC 62 > > > +#define MT6370_IRQ_DIRCHG_OV 63 > > > +#define MT6370_IRQ_OVPCTRL_SWON 67 > > > +#define MT6370_IRQ_OVPCTRL_UVP_D 68 > > > +#define MT6370_IRQ_OVPCTRL_UVP 69 > > > +#define MT6370_IRQ_OVPCTRL_OVP_D 70 > > > +#define MT6370_IRQ_OVPCTRL_OVP 71 > > > +#define MT6370_IRQ_FLED_STRBPIN 72 > > > +#define MT6370_IRQ_FLED_TORPIN 73 > > > +#define MT6370_IRQ_FLED_TX 74 > > > +#define MT6370_IRQ_FLED_LVF 75 > > > +#define MT6370_IRQ_FLED2_SHORT 78 > > > +#define MT6370_IRQ_FLED1_SHORT 79 > > > +#define MT6370_IRQ_FLED2_STRB 80 > > > +#define MT6370_IRQ_FLED1_STRB 81 > > > +#define mT6370_IRQ_FLED2_STRB_TO 82 > > > +#define MT6370_IRQ_FLED1_STRB_TO 83 > > > +#define MT6370_IRQ_FLED2_TOR 84 > > > +#define MT6370_IRQ_FLED1_TOR 85 > > > +#define MT6370_IRQ_OTP 93 > > > +#define MT6370_IRQ_VDDA_OVP 94 > > > +#define MT6370_IRQ_VDDA_UV 95 > > > +#define MT6370_IRQ_LDO_OC 103 > > > +#define MT6370_IRQ_BLED_OCP 118 > > > +#define MT6370_IRQ_BLED_OVP 119 > > > +#define MT6370_IRQ_DSV_VNEG_OCP 123 > > > +#define MT6370_IRQ_DSV_VPOS_OCP 124 > > > +#define MT6370_IRQ_DSV_BST_OCP 125 > > > +#define MT6370_IRQ_DSV_VNEG_SCP 126 > > > +#define MT6370_IRQ_DSV_VPOS_SCP 127 > > > + > > > +struct mt6370_info { > > > + struct i2c_client *i2c[MT6370_MAX_I2C]; > > > + struct device *dev; > > > + struct regmap *regmap; > > > + struct regmap_irq_chip_data *irq_data; > > > +}; > > > > Can we shove all of the above into a header file? > > Well... In Patch v1, we put these "#define IRQ" into > "include/dt-bindings/mfd/mediatek,mt6370.h". > But the reviewer of DT files hoped us to remove this header file, we > put these "#define IRQ" in this .c file. > Shall we leave them here or put them into the header file in > "driver/power/supply/mt6370-charger.h"? Where are they used? -- Lee Jones [李琼斯] Principal Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog