From: Corentin Labbe <clabbe.montjoie@gmail.com>
To: linux-aspeed@lists.ozlabs.org
Subject: [PATCH v6 1/5] crypto: aspeed: Add HACE hash driver
Date: Wed, 29 Jun 2022 14:36:20 +0200 [thread overview]
Message-ID: <YrxHRMoMYW+QDSnd@Red> (raw)
In-Reply-To: <20220629094426.1930589-2-neal_liu@aspeedtech.com>
Le Wed, Jun 29, 2022 at 05:44:22PM +0800, Neal Liu a ?crit :
> Hash and Crypto Engine (HACE) is designed to accelerate the
> throughput of hash data digest, encryption, and decryption.
>
> Basically, HACE can be divided into two independently engines
> - Hash Engine and Crypto Engine. This patch aims to add HACE
> hash engine driver for hash accelerator.
>
> Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
> ---
Hello
I have some minor comments below.
> +++ b/drivers/crypto/aspeed/aspeed-hace-hash.c
> @@ -0,0 +1,1428 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Aspeed Technology Inc.
> + */
> +
> +#include "aspeed-hace.h"
> +
> +#ifdef ASPEED_AHASH_DEBUG
> +#define AHASH_DBG(h, fmt, ...) \
> + dev_dbg((h)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
> +#else
> +#define AHASH_DBG(h, fmt, ...) \
> + ((void)(h))
> +#endif
Hello why not direclty use dev_dbg ?
You will still need something to do to enable dev_dbg, so why force to add the need to re-compile it with ASPEED_AHASH_DEBUG ?
[...]
> + if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) {
> + dev_warn(hace_dev->dev, "dma_map() rctx digest error\n");
> + return -ENOMEM;
> + }
An error displayed as warning.
[...]
> + if (!sg_len) {
> + dev_warn(hace_dev->dev, "dma_map_sg() src error\n");
Same here. In fact you have lot of error displayed as warning in the driver.
[...]
> +/* Weak function for HACE hash */
> +void __weak aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev)
> +{
> + pr_warn("%s: Not supported yet\n", __func__);
> +}
> +
> +void __weak aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev)
> +{
> + pr_warn("%s: Not supported yet\n", __func__);
> +}
Why not use dev_warn ?
[...]
> +struct aspeed_sg_list {
> + u32 len;
> + u32 phy_addr;
> +};
Since it is a descriptor where all member are written with cpu_to_le32(), it should be __le32.
Regards
WARNING: multiple messages have this Message-ID (diff)
From: Corentin Labbe <clabbe.montjoie@gmail.com>
To: Neal Liu <neal_liu@aspeedtech.com>
Cc: Christophe JAILLET <christophe.jaillet@wanadoo.fr>,
Randy Dunlap <rdunlap@infradead.org>,
Herbert Xu <herbert@gondor.apana.org.au>,
"David S . Miller" <davem@davemloft.net>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Joel Stanley <joel@jms.id.au>, Andrew Jeffery <andrew@aj.id.au>,
Dhananjay Phadke <dhphadke@microsoft.com>,
Johnny Huang <johnny_huang@aspeedtech.com>,
linux-aspeed@lists.ozlabs.org, linux-crypto@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, BMC-SW@aspeedtech.com
Subject: Re: [PATCH v6 1/5] crypto: aspeed: Add HACE hash driver
Date: Wed, 29 Jun 2022 14:36:20 +0200 [thread overview]
Message-ID: <YrxHRMoMYW+QDSnd@Red> (raw)
In-Reply-To: <20220629094426.1930589-2-neal_liu@aspeedtech.com>
Le Wed, Jun 29, 2022 at 05:44:22PM +0800, Neal Liu a écrit :
> Hash and Crypto Engine (HACE) is designed to accelerate the
> throughput of hash data digest, encryption, and decryption.
>
> Basically, HACE can be divided into two independently engines
> - Hash Engine and Crypto Engine. This patch aims to add HACE
> hash engine driver for hash accelerator.
>
> Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
> ---
Hello
I have some minor comments below.
> +++ b/drivers/crypto/aspeed/aspeed-hace-hash.c
> @@ -0,0 +1,1428 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Aspeed Technology Inc.
> + */
> +
> +#include "aspeed-hace.h"
> +
> +#ifdef ASPEED_AHASH_DEBUG
> +#define AHASH_DBG(h, fmt, ...) \
> + dev_dbg((h)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
> +#else
> +#define AHASH_DBG(h, fmt, ...) \
> + ((void)(h))
> +#endif
Hello why not direclty use dev_dbg ?
You will still need something to do to enable dev_dbg, so why force to add the need to re-compile it with ASPEED_AHASH_DEBUG ?
[...]
> + if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) {
> + dev_warn(hace_dev->dev, "dma_map() rctx digest error\n");
> + return -ENOMEM;
> + }
An error displayed as warning.
[...]
> + if (!sg_len) {
> + dev_warn(hace_dev->dev, "dma_map_sg() src error\n");
Same here. In fact you have lot of error displayed as warning in the driver.
[...]
> +/* Weak function for HACE hash */
> +void __weak aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev)
> +{
> + pr_warn("%s: Not supported yet\n", __func__);
> +}
> +
> +void __weak aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev)
> +{
> + pr_warn("%s: Not supported yet\n", __func__);
> +}
Why not use dev_warn ?
[...]
> +struct aspeed_sg_list {
> + u32 len;
> + u32 phy_addr;
> +};
Since it is a descriptor where all member are written with cpu_to_le32(), it should be __le32.
Regards
WARNING: multiple messages have this Message-ID (diff)
From: Corentin Labbe <clabbe.montjoie@gmail.com>
To: Neal Liu <neal_liu@aspeedtech.com>
Cc: Christophe JAILLET <christophe.jaillet@wanadoo.fr>,
Randy Dunlap <rdunlap@infradead.org>,
Herbert Xu <herbert@gondor.apana.org.au>,
"David S . Miller" <davem@davemloft.net>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Joel Stanley <joel@jms.id.au>, Andrew Jeffery <andrew@aj.id.au>,
Dhananjay Phadke <dhphadke@microsoft.com>,
Johnny Huang <johnny_huang@aspeedtech.com>,
linux-aspeed@lists.ozlabs.org, linux-crypto@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, BMC-SW@aspeedtech.com
Subject: Re: [PATCH v6 1/5] crypto: aspeed: Add HACE hash driver
Date: Wed, 29 Jun 2022 14:36:20 +0200 [thread overview]
Message-ID: <YrxHRMoMYW+QDSnd@Red> (raw)
In-Reply-To: <20220629094426.1930589-2-neal_liu@aspeedtech.com>
Le Wed, Jun 29, 2022 at 05:44:22PM +0800, Neal Liu a écrit :
> Hash and Crypto Engine (HACE) is designed to accelerate the
> throughput of hash data digest, encryption, and decryption.
>
> Basically, HACE can be divided into two independently engines
> - Hash Engine and Crypto Engine. This patch aims to add HACE
> hash engine driver for hash accelerator.
>
> Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
> ---
Hello
I have some minor comments below.
> +++ b/drivers/crypto/aspeed/aspeed-hace-hash.c
> @@ -0,0 +1,1428 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Aspeed Technology Inc.
> + */
> +
> +#include "aspeed-hace.h"
> +
> +#ifdef ASPEED_AHASH_DEBUG
> +#define AHASH_DBG(h, fmt, ...) \
> + dev_dbg((h)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
> +#else
> +#define AHASH_DBG(h, fmt, ...) \
> + ((void)(h))
> +#endif
Hello why not direclty use dev_dbg ?
You will still need something to do to enable dev_dbg, so why force to add the need to re-compile it with ASPEED_AHASH_DEBUG ?
[...]
> + if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) {
> + dev_warn(hace_dev->dev, "dma_map() rctx digest error\n");
> + return -ENOMEM;
> + }
An error displayed as warning.
[...]
> + if (!sg_len) {
> + dev_warn(hace_dev->dev, "dma_map_sg() src error\n");
Same here. In fact you have lot of error displayed as warning in the driver.
[...]
> +/* Weak function for HACE hash */
> +void __weak aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev)
> +{
> + pr_warn("%s: Not supported yet\n", __func__);
> +}
> +
> +void __weak aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev)
> +{
> + pr_warn("%s: Not supported yet\n", __func__);
> +}
Why not use dev_warn ?
[...]
> +struct aspeed_sg_list {
> + u32 len;
> + u32 phy_addr;
> +};
Since it is a descriptor where all member are written with cpu_to_le32(), it should be __le32.
Regards
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next prev parent reply other threads:[~2022-06-29 12:36 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-29 9:44 [PATCH v6 0/5] Add Aspeed crypto driver for hardware acceleration Neal Liu
2022-06-29 9:44 ` Neal Liu
2022-06-29 9:44 ` Neal Liu
2022-06-29 9:44 ` [PATCH v6 1/5] crypto: aspeed: Add HACE hash driver Neal Liu
2022-06-29 9:45 ` Neal Liu
2022-06-29 9:44 ` Neal Liu
2022-06-29 12:36 ` Corentin Labbe [this message]
2022-06-29 12:36 ` Corentin Labbe
2022-06-29 12:36 ` Corentin Labbe
2022-06-30 3:41 ` Neal Liu
2022-06-30 3:41 ` Neal Liu
2022-06-30 3:41 ` Neal Liu
2022-06-29 9:44 ` [PATCH v6 2/5] dt-bindings: clock: Add AST2500/AST2600 HACE reset definition Neal Liu
2022-06-29 9:44 ` Neal Liu
2022-06-29 9:44 ` Neal Liu
2022-06-29 11:13 ` Krzysztof Kozlowski
2022-06-29 11:13 ` Krzysztof Kozlowski
2022-06-29 11:13 ` Krzysztof Kozlowski
2022-06-29 11:49 ` Dhananjay Phadke
2022-06-29 11:49 ` Dhananjay Phadke
2022-06-29 11:49 ` Dhananjay Phadke
2022-06-30 3:17 ` Neal Liu
2022-06-30 3:17 ` Neal Liu
2022-06-30 3:17 ` Neal Liu
2022-06-30 3:32 ` Dhananjay Phadke
2022-06-30 3:32 ` Dhananjay Phadke
2022-06-30 3:32 ` Dhananjay Phadke
2022-06-30 7:12 ` Neal Liu
2022-06-30 7:12 ` Neal Liu
2022-06-30 7:12 ` Neal Liu
2022-06-29 9:44 ` [PATCH v6 3/5] ARM: dts: aspeed: Add HACE device controller node Neal Liu
2022-06-29 9:44 ` Neal Liu
2022-06-29 9:44 ` Neal Liu
2022-06-29 9:44 ` [PATCH v6 4/5] dt-bindings: crypto: add documentation for aspeed hace Neal Liu
2022-06-29 9:44 ` Neal Liu
2022-06-29 9:44 ` Neal Liu
2022-06-29 9:44 ` [PATCH v6 5/5] crypto: aspeed: add HACE crypto driver Neal Liu
2022-06-29 9:46 ` Neal Liu
2022-06-29 9:44 ` Neal Liu
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