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[35.230.65.123]) by smtp.gmail.com with ESMTPSA id b9-20020a631b49000000b00411bbcdfbf7sm11659410pgm.87.2022.07.06.10.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 10:52:46 -0700 (PDT) Date: Wed, 6 Jul 2022 17:52:42 +0000 From: Sean Christopherson To: Jim Mattson Cc: Maxim Levitsky , Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Oliver Upton , Peter Shier Subject: Re: [PATCH v2 00/21] KVM: x86: Event/exception fixes and cleanups Message-ID: References: <20220614204730.3359543-1-seanjc@google.com> <7e05e0befa13af05f1e5f0fd8658bc4e7bdf764f.camel@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, Jul 06, 2022, Jim Mattson wrote: > On Wed, Jul 6, 2022 at 4:55 AM Maxim Levitsky wrote: > > > 1. Since #SMI is higher priority than the #MTF, that means that unless dual monitor treatment is used, > > and the dual monitor handler figures out that #MTF was pending and re-injects it when it > > VMRESUME's the 'host', the MTF gets lost, and there is no way for a normal hypervisor to > > do anything about it. > > > > Or maybe pending MTF is saved to SMRAM somewhere. > > > > In case you will say that I am inventing this again, I am saying now that the above is > > just a guess. > > This is covered in the SDM, volume 3, section 31.14.1: "Default > Treatment of SMI Delivery:" > > The pseudocode above makes reference to the saving of VMX-critical > state. This state consists of the following: > (1) SS.DPL (the current privilege level); (2) RFLAGS.VM2; (3) the > state of blocking by STI and by MOV SS (see > Table 24-3 in Section 24.4.2); (4) the state of virtual-NMI blocking > (only if the processor is in VMX non-root oper- > ation and the “virtual NMIs” VM-execution control is 1); and (5) an > indication of whether an MTF VM exit is pending > (see Section 25.5.2). These data may be saved internal to the > processor or in the VMCS region of the current > VMCS. Processors that do not support SMI recognition while there is > blocking by STI or by MOV SS need not save > the state of such blocking. > > Saving VMX-critical state to SMRAM is not documented as an option. Hmm, I'm not entirely convinced that Intel doesn't interpret "internal to the processor" as "undocumented SMRAM fields". But I could also be misremembering the SMI flows. Regardless, I do like the idea of using vmcs12 instead of SMRAM. That would provide some extra motivation for moving away from KVM's broken pseudo VM-Exit implementation.