Re: [PATCH] i2c: cadence: Change large transfer count reset logic to be unconditional

[Wolfram Sang <wsa@kernel.org>]

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On Tue, Jun 14, 2022 at 05:29:19PM -0600, Robert Hancock wrote:
> Problems were observed on the Xilinx ZynqMP platform with large I2C reads.
> When a read of 277 bytes was performed, the controller NAKed the transfer
> after only 252 bytes were transferred and returned an ENXIO error on the
> transfer.
> 
> There is some code in cdns_i2c_master_isr to handle this case by resetting
> the transfer count in the controller before it reaches 0, to allow larger
> transfers to work, but it was conditional on the CDNS_I2C_BROKEN_HOLD_BIT
> quirk being set on the controller, and ZynqMP uses the r1p14 version of
> the core where this quirk is not being set. The requirement to do this to
> support larger reads seems like an inherently required workaround due to
> the core only having an 8-bit transfer size register, so it does not
> appear that this should be conditional on the broken HOLD bit quirk which
> is used elsewhere in the driver.
> 
> Remove the dependency on the CDNS_I2C_BROKEN_HOLD_BIT for this transfer
> size reset logic to fix this problem.
> 
> Fixes: 63cab195bf49 ("i2c: removed work arounds in i2c driver for Zynq Ultrascale+ MPSoC")
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>

Applied to for-current, thanks!


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