From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BB13C19F2A for ; Sun, 7 Aug 2022 12:51:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4Z1eD6pnc+C8V0Z3pmPVObONr6Ws6Xg1hQ3wGrzzbaA=; b=a2att6pPXrIAvi SzavuA27kCunjiumpHsLx+25TXlBxMiGNP6P9cyf6EVg9Fjpe32PF39J7wFNBNEh0r8xFl6thCcig xTpH/glwUTQTCo85fkxUmzC7IIN0X6MnojeOl6BNt/2OOsJGIJ91rx+8J5R44gP8fUpOLpQW6fDEq USmo5eSQZu2OD9okRYITAbgtxeqGmzBrQ2ptnI8CGC1tZIwoB5X/4GTUJ18Im0yCWlPgRjz6V95VS R7ve28cR5uk8tDcQTzvG+kN99nBiLULhu6xltz1f76zK9yBAot3GE9jkUoNlstPQ0gmKtE5aPEWiP AEccOZJtXRqyn5QDj7ww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oKfkV-00CJYP-FV; Sun, 07 Aug 2022 12:51:19 +0000 Received: from static-213-198-238-194.adsl.eunet.rs ([213.198.238.194] helo=fx.arvanta.net) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oKfkI-00CJLU-SJ; Sun, 07 Aug 2022 12:51:08 +0000 Received: from m1 (kcl.arvanta.net [10.5.1.8]) by fx.arvanta.net (Postfix) with ESMTP id 6A11625185; Sun, 7 Aug 2022 14:38:37 +0200 (CEST) Date: Sun, 7 Aug 2022 14:38:52 +0200 From: Milan =?utf-8?Q?P=2E_Stani=C4=87?= To: Hugh Cole-Baker Cc: heiko@sntech.de, hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com Subject: Re: [PATCH v2 1/3] drm/rockchip: define gamma registers for RK3399 Message-ID: References: <20211019215843.42718-1-sigmaris@gmail.com> <20211019215843.42718-2-sigmaris@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211019215843.42718-2-sigmaris@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220807_055107_173132_3E61CA18 X-CRM114-Status: GOOD ( 18.38 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org SGksCgpUZXN0ZWQgaXQgb24gZ3J1LWtldmluIHdpdGggbWFpbmxpbmUga2VybmVsIDUuMTkgYW5k IGl0IHdvcmtzCgpPbiBUdWUsIDIwMjEtMTAtMTkgYXQgMjI6NTgsIEh1Z2ggQ29sZS1CYWtlciB3 cm90ZToKPiBUaGUgVk9QIG9uIFJLMzM5OSBoYXMgYSBkaWZmZXJlbnQgYXBwcm9hY2ggZnJvbSBw cmV2aW91cyB2ZXJzaW9ucyBmb3IKPiBzZXR0aW5nIGEgZ2FtbWEgbG9va3VwIHRhYmxlLCB1c2lu ZyBhbiB1cGRhdGVfZ2FtbWFfbHV0IHJlZ2lzdGVyLiBBcwo+IHRoaXMgZGlmZmVycyBmcm9tIFJL MzI4OCwgZ2l2ZSBSSzMzOTkgaXRzIG93biBzZXQgb2YgImNvbW1vbiIgcmVnaXN0ZXIKPiBkZWZp bml0aW9ucy4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBIdWdoIENvbGUtQmFrZXIgPHNpZ21hcmlzQGdt YWlsLmNvbT4KVGVzdGVkLWJ5OiAiTWlsYW4gUC4gU3RhbmnEhyIgPG1wc0BhcnZhbnRhLm5ldD4K PiAtLS0KPiAKPiBDaGFuZ2VzIGZyb20gdjE6IG5vIGNoYW5nZXMgaW4gdGhpcyBwYXRjaAo+IAo+ ICBkcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX3ZvcC5oIHwgIDIgKysKPiAg ZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuYyB8IDI0ICsrKysrKysr KysrKysrKysrKystLQo+ICBkcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfdm9wX3Jl Zy5oIHwgIDEgKwo+ICAzIGZpbGVzIGNoYW5nZWQsIDI1IGluc2VydGlvbnMoKyksIDIgZGVsZXRp b25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hp cF9kcm1fdm9wLmggYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX3ZvcC5o Cj4gaW5kZXggODU3ZDk3Y2RjNjdjLi4xNDE3OWU4OWJkMjEgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVy cy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2RybV92b3AuaAo+ICsrKyBiL2RyaXZlcnMvZ3B1 L2RybS9yb2NrY2hpcC9yb2NrY2hpcF9kcm1fdm9wLmgKPiBAQCAtOTksNiArOTksOCBAQCBzdHJ1 Y3Qgdm9wX2NvbW1vbiB7Cj4gIAlzdHJ1Y3Qgdm9wX3JlZyBkaXRoZXJfZG93bl9lbjsKPiAgCXN0 cnVjdCB2b3BfcmVnIGRpdGhlcl91cDsKPiAgCXN0cnVjdCB2b3BfcmVnIGRzcF9sdXRfZW47Cj4g KwlzdHJ1Y3Qgdm9wX3JlZyB1cGRhdGVfZ2FtbWFfbHV0Owo+ICsJc3RydWN0IHZvcF9yZWcgbHV0 X2J1ZmZlcl9pbmRleDsKPiAgCXN0cnVjdCB2b3BfcmVnIGdhdGVfZW47Cj4gIAlzdHJ1Y3Qgdm9w X3JlZyBtbXVfZW47Cj4gIAlzdHJ1Y3Qgdm9wX3JlZyBvdXRfbW9kZTsKPiBkaWZmIC0tZ2l0IGEv ZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuYyBiL2RyaXZlcnMvZ3B1 L2RybS9yb2NrY2hpcC9yb2NrY2hpcF92b3BfcmVnLmMKPiBpbmRleCBjYTdjYzgyMTI1Y2IuLmJm YjdlMTMwZjA5YiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2No aXBfdm9wX3JlZy5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3Zv cF9yZWcuYwo+IEBAIC04NjUsNiArODY1LDI0IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9wX291 dHB1dCByazMzOTlfb3V0cHV0ID0gewo+ICAJLm1pcGlfZHVhbF9jaGFubmVsX2VuID0gVk9QX1JF RyhSSzMyODhfU1lTX0NUUkwsIDB4MSwgMyksCj4gIH07Cj4gIAo+ICtzdGF0aWMgY29uc3Qgc3Ry dWN0IHZvcF9jb21tb24gcmszMzk5X2NvbW1vbiA9IHsKPiArCS5zdGFuZGJ5ID0gVk9QX1JFR19T WU5DKFJLMzM5OV9TWVNfQ1RSTCwgMHgxLCAyMiksCj4gKwkuZ2F0ZV9lbiA9IFZPUF9SRUcoUksz Mzk5X1NZU19DVFJMLCAweDEsIDIzKSwKPiArCS5tbXVfZW4gPSBWT1BfUkVHKFJLMzM5OV9TWVNf Q1RSTCwgMHgxLCAyMCksCj4gKwkuZGl0aGVyX2Rvd25fc2VsID0gVk9QX1JFRyhSSzMzOTlfRFNQ X0NUUkwxLCAweDEsIDQpLAo+ICsJLmRpdGhlcl9kb3duX21vZGUgPSBWT1BfUkVHKFJLMzM5OV9E U1BfQ1RSTDEsIDB4MSwgMyksCj4gKwkuZGl0aGVyX2Rvd25fZW4gPSBWT1BfUkVHKFJLMzM5OV9E U1BfQ1RSTDEsIDB4MSwgMiksCj4gKwkucHJlX2RpdGhlcl9kb3duID0gVk9QX1JFRyhSSzMzOTlf RFNQX0NUUkwxLCAweDEsIDEpLAo+ICsJLmRpdGhlcl91cCA9IFZPUF9SRUcoUkszMzk5X0RTUF9D VFJMMSwgMHgxLCA2KSwKPiArCS5kc3BfbHV0X2VuID0gVk9QX1JFRyhSSzMzOTlfRFNQX0NUUkwx LCAweDEsIDApLAo+ICsJLnVwZGF0ZV9nYW1tYV9sdXQgPSBWT1BfUkVHKFJLMzM5OV9EU1BfQ1RS TDEsIDB4MSwgNyksCj4gKwkubHV0X2J1ZmZlcl9pbmRleCA9IFZPUF9SRUcoUkszMzk5X0RCR19Q T1NUX1JFRzEsIDB4MSwgMSksCj4gKwkuZGF0YV9ibGFuayA9IFZPUF9SRUcoUkszMzk5X0RTUF9D VFJMMCwgMHgxLCAxOSksCj4gKwkuZHNwX2JsYW5rID0gVk9QX1JFRyhSSzMzOTlfRFNQX0NUUkww LCAweDMsIDE4KSwKPiArCS5vdXRfbW9kZSA9IFZPUF9SRUcoUkszMzk5X0RTUF9DVFJMMCwgMHhm LCAwKSwKPiArCS5jZmdfZG9uZSA9IFZPUF9SRUdfU1lOQyhSSzMzOTlfUkVHX0NGR19ET05FLCAw eDEsIDApLAo+ICt9Owo+ICsKPiAgc3RhdGljIGNvbnN0IHN0cnVjdCB2b3BfeXV2Mnl1dl9waHkg cmszMzk5X3l1djJ5dXZfd2luMDFfZGF0YSA9IHsKPiAgCS55MnJfY29lZmZpY2llbnRzID0gewo+ ICAJCVZPUF9SRUcoUkszMzk5X1dJTjBfWVVWMllVVl9ZMlIgKyAwLCAweGZmZmYsIDApLAo+IEBA IC05NDQsNyArOTYyLDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCB2b3BfZGF0YSByazMzOTlfdm9w X2JpZyA9IHsKPiAgCS52ZXJzaW9uID0gVk9QX1ZFUlNJT04oMywgNSksCj4gIAkuZmVhdHVyZSA9 IFZPUF9GRUFUVVJFX09VVFBVVF9SR0IxMCwKPiAgCS5pbnRyID0gJnJrMzM2Nl92b3BfaW50ciwK PiAtCS5jb21tb24gPSAmcmszMjg4X2NvbW1vbiwKPiArCS5jb21tb24gPSAmcmszMzk5X2NvbW1v biwKPiAgCS5tb2Rlc2V0ID0gJnJrMzI4OF9tb2Rlc2V0LAo+ICAJLm91dHB1dCA9ICZyazMzOTlf b3V0cHV0LAo+ICAJLmFmYmMgPSAmcmszMzk5X3ZvcF9hZmJjLAo+IEBAIC05NTIsNiArOTcwLDcg QEAgc3RhdGljIGNvbnN0IHN0cnVjdCB2b3BfZGF0YSByazMzOTlfdm9wX2JpZyA9IHsKPiAgCS53 aW4gPSByazMzOTlfdm9wX3dpbl9kYXRhLAo+ICAJLndpbl9zaXplID0gQVJSQVlfU0laRShyazMz OTlfdm9wX3dpbl9kYXRhKSwKPiAgCS53aW5feXV2Mnl1diA9IHJrMzM5OV92b3BfYmlnX3dpbl95 dXYyeXV2X2RhdGEsCj4gKwkubHV0X3NpemUgPSAxMDI0LAo+ICB9Owo+ICAKPiAgc3RhdGljIGNv bnN0IHN0cnVjdCB2b3Bfd2luX2RhdGEgcmszMzk5X3ZvcF9saXRfd2luX2RhdGFbXSA9IHsKPiBA QCAtOTcwLDEzICs5ODksMTQgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCB2b3Bfd2luX3l1djJ5dXZf ZGF0YSByazMzOTlfdm9wX2xpdF93aW5feXV2Mnl1dl9kYXRhW10gPSB7Cj4gIHN0YXRpYyBjb25z dCBzdHJ1Y3Qgdm9wX2RhdGEgcmszMzk5X3ZvcF9saXQgPSB7Cj4gIAkudmVyc2lvbiA9IFZPUF9W RVJTSU9OKDMsIDYpLAo+ICAJLmludHIgPSAmcmszMzY2X3ZvcF9pbnRyLAo+IC0JLmNvbW1vbiA9 ICZyazMyODhfY29tbW9uLAo+ICsJLmNvbW1vbiA9ICZyazMzOTlfY29tbW9uLAo+ICAJLm1vZGVz ZXQgPSAmcmszMjg4X21vZGVzZXQsCj4gIAkub3V0cHV0ID0gJnJrMzM5OV9vdXRwdXQsCj4gIAku bWlzYyA9ICZyazMzNjhfbWlzYywKPiAgCS53aW4gPSByazMzOTlfdm9wX2xpdF93aW5fZGF0YSwK PiAgCS53aW5fc2l6ZSA9IEFSUkFZX1NJWkUocmszMzk5X3ZvcF9saXRfd2luX2RhdGEpLAo+ICAJ Lndpbl95dXYyeXV2ID0gcmszMzk5X3ZvcF9saXRfd2luX3l1djJ5dXZfZGF0YSwKPiArCS5sdXRf c2l6ZSA9IDI1NiwKPiAgfTsKPiAgCj4gIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9wX3dpbl9kYXRh IHJrMzIyOF92b3Bfd2luX2RhdGFbXSA9IHsKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJt L3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuaCBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9y b2NrY2hpcF92b3BfcmVnLmgKPiBpbmRleCAwYjNjZDY1YmE1YzEuLjQwNmU5ODFjNzViZCAxMDA2 NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfdm9wX3JlZy5oCj4g KysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuaAo+IEBAIC02 MjgsNiArNjI4LDcgQEAKPiAgI2RlZmluZSBSSzMzOTlfWVVWMllVVl9XSU4JCQkweDAyYzAKPiAg I2RlZmluZSBSSzMzOTlfWVVWMllVVl9QT1NUCQkJMHgwMmM0Cj4gICNkZWZpbmUgUkszMzk5X0FV VE9fR0FUSU5HX0VOCQkJMHgwMmNjCj4gKyNkZWZpbmUgUkszMzk5X0RCR19QT1NUX1JFRzEJCQkw eDAzNmMKPiAgI2RlZmluZSBSSzMzOTlfV0lOMF9DU0NfQ09FCQkJMHgwM2EwCj4gICNkZWZpbmUg UkszMzk5X1dJTjFfQ1NDX0NPRQkJCTB4MDNjMAo+ICAjZGVmaW5lIFJLMzM5OV9XSU4yX0NTQ19D T0UJCQkweDAzZTAKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fCkxpbnV4LXJvY2tjaGlwIG1haWxpbmcgbGlzdApMaW51eC1yb2NrY2hpcEBsaXN0cy5pbmZy YWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGlu dXgtcm9ja2NoaXAK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A565AC19F2A for ; Sun, 7 Aug 2022 12:52:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QhteNhVdfGj7gFisk4HtdmG2iZ9LNqyOXFI+/RZl30Q=; b=OZAWfmtBP2PFyp 0be1cGlukp/9ZL3bN6//ynaQ0EQ1jbwijx07pVsor36K16rLg0dHLDkYZkrBK4LOp7o/6UepTKhNy pAkapgsm3xRwuLPk3NWcyVdJB0wVF9eIJ6zj6Q6F8Ghof8Y5HNXWusZ6eBH73BTj0JYWrQtSX9KCE 7I6+bcub1J/eWNFt9UR0izYwrUufZtlGVXnXtmF5hc3MKWzteX2X4pAJlJ0qOp1M6zV46dLEjrsgP EMk3FdwucBSFN1rhSo1stbCKvgITg30NkxsWY9TYUhifNj5gDAv77d80ItsU32fdHAHCuVeIrHDXB SG20RJZNreY/LsViEnMA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oKfkN-00CJRh-8t; Sun, 07 Aug 2022 12:51:11 +0000 Received: from static-213-198-238-194.adsl.eunet.rs ([213.198.238.194] helo=fx.arvanta.net) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oKfkI-00CJLU-SJ; Sun, 07 Aug 2022 12:51:08 +0000 Received: from m1 (kcl.arvanta.net [10.5.1.8]) by fx.arvanta.net (Postfix) with ESMTP id 6A11625185; Sun, 7 Aug 2022 14:38:37 +0200 (CEST) Date: Sun, 7 Aug 2022 14:38:52 +0200 From: Milan =?utf-8?Q?P=2E_Stani=C4=87?= To: Hugh Cole-Baker Cc: heiko@sntech.de, hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com Subject: Re: [PATCH v2 1/3] drm/rockchip: define gamma registers for RK3399 Message-ID: References: <20211019215843.42718-1-sigmaris@gmail.com> <20211019215843.42718-2-sigmaris@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211019215843.42718-2-sigmaris@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220807_055107_173132_3E61CA18 X-CRM114-Status: GOOD ( 18.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGksCgpUZXN0ZWQgaXQgb24gZ3J1LWtldmluIHdpdGggbWFpbmxpbmUga2VybmVsIDUuMTkgYW5k IGl0IHdvcmtzCgpPbiBUdWUsIDIwMjEtMTAtMTkgYXQgMjI6NTgsIEh1Z2ggQ29sZS1CYWtlciB3 cm90ZToKPiBUaGUgVk9QIG9uIFJLMzM5OSBoYXMgYSBkaWZmZXJlbnQgYXBwcm9hY2ggZnJvbSBw cmV2aW91cyB2ZXJzaW9ucyBmb3IKPiBzZXR0aW5nIGEgZ2FtbWEgbG9va3VwIHRhYmxlLCB1c2lu ZyBhbiB1cGRhdGVfZ2FtbWFfbHV0IHJlZ2lzdGVyLiBBcwo+IHRoaXMgZGlmZmVycyBmcm9tIFJL MzI4OCwgZ2l2ZSBSSzMzOTkgaXRzIG93biBzZXQgb2YgImNvbW1vbiIgcmVnaXN0ZXIKPiBkZWZp bml0aW9ucy4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBIdWdoIENvbGUtQmFrZXIgPHNpZ21hcmlzQGdt YWlsLmNvbT4KVGVzdGVkLWJ5OiAiTWlsYW4gUC4gU3RhbmnEhyIgPG1wc0BhcnZhbnRhLm5ldD4K PiAtLS0KPiAKPiBDaGFuZ2VzIGZyb20gdjE6IG5vIGNoYW5nZXMgaW4gdGhpcyBwYXRjaAo+IAo+ ICBkcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX3ZvcC5oIHwgIDIgKysKPiAg ZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuYyB8IDI0ICsrKysrKysr KysrKysrKysrKystLQo+ICBkcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfdm9wX3Jl Zy5oIHwgIDEgKwo+ICAzIGZpbGVzIGNoYW5nZWQsIDI1IGluc2VydGlvbnMoKyksIDIgZGVsZXRp b25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hp cF9kcm1fdm9wLmggYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX3ZvcC5o Cj4gaW5kZXggODU3ZDk3Y2RjNjdjLi4xNDE3OWU4OWJkMjEgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVy cy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2RybV92b3AuaAo+ICsrKyBiL2RyaXZlcnMvZ3B1 L2RybS9yb2NrY2hpcC9yb2NrY2hpcF9kcm1fdm9wLmgKPiBAQCAtOTksNiArOTksOCBAQCBzdHJ1 Y3Qgdm9wX2NvbW1vbiB7Cj4gIAlzdHJ1Y3Qgdm9wX3JlZyBkaXRoZXJfZG93bl9lbjsKPiAgCXN0 cnVjdCB2b3BfcmVnIGRpdGhlcl91cDsKPiAgCXN0cnVjdCB2b3BfcmVnIGRzcF9sdXRfZW47Cj4g KwlzdHJ1Y3Qgdm9wX3JlZyB1cGRhdGVfZ2FtbWFfbHV0Owo+ICsJc3RydWN0IHZvcF9yZWcgbHV0 X2J1ZmZlcl9pbmRleDsKPiAgCXN0cnVjdCB2b3BfcmVnIGdhdGVfZW47Cj4gIAlzdHJ1Y3Qgdm9w X3JlZyBtbXVfZW47Cj4gIAlzdHJ1Y3Qgdm9wX3JlZyBvdXRfbW9kZTsKPiBkaWZmIC0tZ2l0IGEv ZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuYyBiL2RyaXZlcnMvZ3B1 L2RybS9yb2NrY2hpcC9yb2NrY2hpcF92b3BfcmVnLmMKPiBpbmRleCBjYTdjYzgyMTI1Y2IuLmJm YjdlMTMwZjA5YiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2No aXBfdm9wX3JlZy5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3Zv cF9yZWcuYwo+IEBAIC04NjUsNiArODY1LDI0IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9wX291 dHB1dCByazMzOTlfb3V0cHV0ID0gewo+ICAJLm1pcGlfZHVhbF9jaGFubmVsX2VuID0gVk9QX1JF RyhSSzMyODhfU1lTX0NUUkwsIDB4MSwgMyksCj4gIH07Cj4gIAo+ICtzdGF0aWMgY29uc3Qgc3Ry dWN0IHZvcF9jb21tb24gcmszMzk5X2NvbW1vbiA9IHsKPiArCS5zdGFuZGJ5ID0gVk9QX1JFR19T WU5DKFJLMzM5OV9TWVNfQ1RSTCwgMHgxLCAyMiksCj4gKwkuZ2F0ZV9lbiA9IFZPUF9SRUcoUksz Mzk5X1NZU19DVFJMLCAweDEsIDIzKSwKPiArCS5tbXVfZW4gPSBWT1BfUkVHKFJLMzM5OV9TWVNf Q1RSTCwgMHgxLCAyMCksCj4gKwkuZGl0aGVyX2Rvd25fc2VsID0gVk9QX1JFRyhSSzMzOTlfRFNQ X0NUUkwxLCAweDEsIDQpLAo+ICsJLmRpdGhlcl9kb3duX21vZGUgPSBWT1BfUkVHKFJLMzM5OV9E U1BfQ1RSTDEsIDB4MSwgMyksCj4gKwkuZGl0aGVyX2Rvd25fZW4gPSBWT1BfUkVHKFJLMzM5OV9E U1BfQ1RSTDEsIDB4MSwgMiksCj4gKwkucHJlX2RpdGhlcl9kb3duID0gVk9QX1JFRyhSSzMzOTlf RFNQX0NUUkwxLCAweDEsIDEpLAo+ICsJLmRpdGhlcl91cCA9IFZPUF9SRUcoUkszMzk5X0RTUF9D VFJMMSwgMHgxLCA2KSwKPiArCS5kc3BfbHV0X2VuID0gVk9QX1JFRyhSSzMzOTlfRFNQX0NUUkwx LCAweDEsIDApLAo+ICsJLnVwZGF0ZV9nYW1tYV9sdXQgPSBWT1BfUkVHKFJLMzM5OV9EU1BfQ1RS TDEsIDB4MSwgNyksCj4gKwkubHV0X2J1ZmZlcl9pbmRleCA9IFZPUF9SRUcoUkszMzk5X0RCR19Q T1NUX1JFRzEsIDB4MSwgMSksCj4gKwkuZGF0YV9ibGFuayA9IFZPUF9SRUcoUkszMzk5X0RTUF9D VFJMMCwgMHgxLCAxOSksCj4gKwkuZHNwX2JsYW5rID0gVk9QX1JFRyhSSzMzOTlfRFNQX0NUUkww LCAweDMsIDE4KSwKPiArCS5vdXRfbW9kZSA9IFZPUF9SRUcoUkszMzk5X0RTUF9DVFJMMCwgMHhm LCAwKSwKPiArCS5jZmdfZG9uZSA9IFZPUF9SRUdfU1lOQyhSSzMzOTlfUkVHX0NGR19ET05FLCAw eDEsIDApLAo+ICt9Owo+ICsKPiAgc3RhdGljIGNvbnN0IHN0cnVjdCB2b3BfeXV2Mnl1dl9waHkg cmszMzk5X3l1djJ5dXZfd2luMDFfZGF0YSA9IHsKPiAgCS55MnJfY29lZmZpY2llbnRzID0gewo+ ICAJCVZPUF9SRUcoUkszMzk5X1dJTjBfWVVWMllVVl9ZMlIgKyAwLCAweGZmZmYsIDApLAo+IEBA IC05NDQsNyArOTYyLDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCB2b3BfZGF0YSByazMzOTlfdm9w X2JpZyA9IHsKPiAgCS52ZXJzaW9uID0gVk9QX1ZFUlNJT04oMywgNSksCj4gIAkuZmVhdHVyZSA9 IFZPUF9GRUFUVVJFX09VVFBVVF9SR0IxMCwKPiAgCS5pbnRyID0gJnJrMzM2Nl92b3BfaW50ciwK PiAtCS5jb21tb24gPSAmcmszMjg4X2NvbW1vbiwKPiArCS5jb21tb24gPSAmcmszMzk5X2NvbW1v biwKPiAgCS5tb2Rlc2V0ID0gJnJrMzI4OF9tb2Rlc2V0LAo+ICAJLm91dHB1dCA9ICZyazMzOTlf b3V0cHV0LAo+ICAJLmFmYmMgPSAmcmszMzk5X3ZvcF9hZmJjLAo+IEBAIC05NTIsNiArOTcwLDcg QEAgc3RhdGljIGNvbnN0IHN0cnVjdCB2b3BfZGF0YSByazMzOTlfdm9wX2JpZyA9IHsKPiAgCS53 aW4gPSByazMzOTlfdm9wX3dpbl9kYXRhLAo+ICAJLndpbl9zaXplID0gQVJSQVlfU0laRShyazMz OTlfdm9wX3dpbl9kYXRhKSwKPiAgCS53aW5feXV2Mnl1diA9IHJrMzM5OV92b3BfYmlnX3dpbl95 dXYyeXV2X2RhdGEsCj4gKwkubHV0X3NpemUgPSAxMDI0LAo+ICB9Owo+ICAKPiAgc3RhdGljIGNv bnN0IHN0cnVjdCB2b3Bfd2luX2RhdGEgcmszMzk5X3ZvcF9saXRfd2luX2RhdGFbXSA9IHsKPiBA QCAtOTcwLDEzICs5ODksMTQgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCB2b3Bfd2luX3l1djJ5dXZf ZGF0YSByazMzOTlfdm9wX2xpdF93aW5feXV2Mnl1dl9kYXRhW10gPSB7Cj4gIHN0YXRpYyBjb25z dCBzdHJ1Y3Qgdm9wX2RhdGEgcmszMzk5X3ZvcF9saXQgPSB7Cj4gIAkudmVyc2lvbiA9IFZPUF9W RVJTSU9OKDMsIDYpLAo+ICAJLmludHIgPSAmcmszMzY2X3ZvcF9pbnRyLAo+IC0JLmNvbW1vbiA9 ICZyazMyODhfY29tbW9uLAo+ICsJLmNvbW1vbiA9ICZyazMzOTlfY29tbW9uLAo+ICAJLm1vZGVz ZXQgPSAmcmszMjg4X21vZGVzZXQsCj4gIAkub3V0cHV0ID0gJnJrMzM5OV9vdXRwdXQsCj4gIAku bWlzYyA9ICZyazMzNjhfbWlzYywKPiAgCS53aW4gPSByazMzOTlfdm9wX2xpdF93aW5fZGF0YSwK PiAgCS53aW5fc2l6ZSA9IEFSUkFZX1NJWkUocmszMzk5X3ZvcF9saXRfd2luX2RhdGEpLAo+ICAJ Lndpbl95dXYyeXV2ID0gcmszMzk5X3ZvcF9saXRfd2luX3l1djJ5dXZfZGF0YSwKPiArCS5sdXRf c2l6ZSA9IDI1NiwKPiAgfTsKPiAgCj4gIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9wX3dpbl9kYXRh IHJrMzIyOF92b3Bfd2luX2RhdGFbXSA9IHsKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJt L3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuaCBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9y b2NrY2hpcF92b3BfcmVnLmgKPiBpbmRleCAwYjNjZDY1YmE1YzEuLjQwNmU5ODFjNzViZCAxMDA2 NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfdm9wX3JlZy5oCj4g KysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuaAo+IEBAIC02 MjgsNiArNjI4LDcgQEAKPiAgI2RlZmluZSBSSzMzOTlfWVVWMllVVl9XSU4JCQkweDAyYzAKPiAg I2RlZmluZSBSSzMzOTlfWVVWMllVVl9QT1NUCQkJMHgwMmM0Cj4gICNkZWZpbmUgUkszMzk5X0FV VE9fR0FUSU5HX0VOCQkJMHgwMmNjCj4gKyNkZWZpbmUgUkszMzk5X0RCR19QT1NUX1JFRzEJCQkw eDAzNmMKPiAgI2RlZmluZSBSSzMzOTlfV0lOMF9DU0NfQ09FCQkJMHgwM2EwCj4gICNkZWZpbmUg UkszMzk5X1dJTjFfQ1NDX0NPRQkJCTB4MDNjMAo+ICAjZGVmaW5lIFJLMzM5OV9XSU4yX0NTQ19D T0UJCQkweDAzZTAKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fCmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMu aW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZv L2xpbnV4LWFybS1rZXJuZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06808C19F2A for ; Sun, 7 Aug 2022 14:48:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5AA1A8D4D3; Sun, 7 Aug 2022 14:47:42 +0000 (UTC) X-Greylist: delayed 745 seconds by postgrey-1.36 at gabe; Sun, 07 Aug 2022 12:51:05 UTC Received: from fx.arvanta.net (static-213-198-238-194.adsl.eunet.rs [213.198.238.194]) by gabe.freedesktop.org (Postfix) with ESMTP id 66E4FAE411 for ; Sun, 7 Aug 2022 12:51:05 +0000 (UTC) Received: from m1 (kcl.arvanta.net [10.5.1.8]) by fx.arvanta.net (Postfix) with ESMTP id 6A11625185; Sun, 7 Aug 2022 14:38:37 +0200 (CEST) Date: Sun, 7 Aug 2022 14:38:52 +0200 From: Milan =?utf-8?Q?P=2E_Stani=C4=87?= To: Hugh Cole-Baker Subject: Re: [PATCH v2 1/3] drm/rockchip: define gamma registers for RK3399 Message-ID: References: <20211019215843.42718-1-sigmaris@gmail.com> <20211019215843.42718-2-sigmaris@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211019215843.42718-2-sigmaris@gmail.com> X-Mailman-Approved-At: Sun, 07 Aug 2022 14:47:23 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Tested it on gru-kevin with mainline kernel 5.19 and it works On Tue, 2021-10-19 at 22:58, Hugh Cole-Baker wrote: > The VOP on RK3399 has a different approach from previous versions for > setting a gamma lookup table, using an update_gamma_lut register. As > this differs from RK3288, give RK3399 its own set of "common" register > definitions. > > Signed-off-by: Hugh Cole-Baker Tested-by: "Milan P. Stanić" > --- > > Changes from v1: no changes in this patch > > drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 ++ > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 24 +++++++++++++++++++-- > drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 1 + > 3 files changed, 25 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > index 857d97cdc67c..14179e89bd21 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > @@ -99,6 +99,8 @@ struct vop_common { > struct vop_reg dither_down_en; > struct vop_reg dither_up; > struct vop_reg dsp_lut_en; > + struct vop_reg update_gamma_lut; > + struct vop_reg lut_buffer_index; > struct vop_reg gate_en; > struct vop_reg mmu_en; > struct vop_reg out_mode; > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index ca7cc82125cb..bfb7e130f09b 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -865,6 +865,24 @@ static const struct vop_output rk3399_output = { > .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), > }; > > +static const struct vop_common rk3399_common = { > + .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), > + .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), > + .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20), > + .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4), > + .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3), > + .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2), > + .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1), > + .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), > + .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0), > + .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7), > + .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1), > + .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), > + .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), > + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), > + .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), > +}; > + > static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { > .y2r_coefficients = { > VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0), > @@ -944,7 +962,7 @@ static const struct vop_data rk3399_vop_big = { > .version = VOP_VERSION(3, 5), > .feature = VOP_FEATURE_OUTPUT_RGB10, > .intr = &rk3366_vop_intr, > - .common = &rk3288_common, > + .common = &rk3399_common, > .modeset = &rk3288_modeset, > .output = &rk3399_output, > .afbc = &rk3399_vop_afbc, > @@ -952,6 +970,7 @@ static const struct vop_data rk3399_vop_big = { > .win = rk3399_vop_win_data, > .win_size = ARRAY_SIZE(rk3399_vop_win_data), > .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data, > + .lut_size = 1024, > }; > > static const struct vop_win_data rk3399_vop_lit_win_data[] = { > @@ -970,13 +989,14 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { > static const struct vop_data rk3399_vop_lit = { > .version = VOP_VERSION(3, 6), > .intr = &rk3366_vop_intr, > - .common = &rk3288_common, > + .common = &rk3399_common, > .modeset = &rk3288_modeset, > .output = &rk3399_output, > .misc = &rk3368_misc, > .win = rk3399_vop_lit_win_data, > .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), > .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data, > + .lut_size = 256, > }; > > static const struct vop_win_data rk3228_vop_win_data[] = { > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h > index 0b3cd65ba5c1..406e981c75bd 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h > @@ -628,6 +628,7 @@ > #define RK3399_YUV2YUV_WIN 0x02c0 > #define RK3399_YUV2YUV_POST 0x02c4 > #define RK3399_AUTO_GATING_EN 0x02cc > +#define RK3399_DBG_POST_REG1 0x036c > #define RK3399_WIN0_CSC_COE 0x03a0 > #define RK3399_WIN1_CSC_COE 0x03c0 > #define RK3399_WIN2_CSC_COE 0x03e0