From: Daniel Golle <daniel@makrotopia.org>
To: Weijie Gao <weijie.gao@mediatek.com>
Cc: u-boot@lists.denx.de,
GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
Subject: Re: [PATCH 01/31] arm: mediatek: add support for MediaTek MT7986 SoC
Date: Sat, 6 Aug 2022 18:09:58 +0200 [thread overview]
Message-ID: <Yu6SVnCZe4ZkJbCa@makrotopia.org> (raw)
In-Reply-To: <442667582058b9c079f3b8058183523e642db723.camel@mediatek.com>
Hi Weijie,
I manually fixed the last 3 patches in the series adding support for
newer SoCs to mkimage/mtk_image.
On my BPi-R3 (mt7986a) I was now trying to use mkimage instead of
bromimage in the same way you introduced that option for mt7622[1]:
The resulting bl2.img works fine on SPI-NAND and eMMC, however,
booting from SPI-NOR or SD card doesn't work.
On SPI-NOR:
F0: 102B 0000
FA: 0000 0000
V0: 7027 6006 [0001]
00: 1017 0000
FA: 5100 0000
01: 102A 0001
02: 5100 0000
BP: 2000 00C0 [0001]
EC: 0000 0000 [0000]
T0: 0000 0213 [010F]
System halt!
On SD card:
F0: 102B 0000
FA: 1040 0000
FA: 1040 0000 [0200]
F9: 103F 0000
F3: 1001 0000 [0200]
F3: 1001 0000
F6: 300C 0028
F5: 0000 0000
L0: 8005 0000 [0001]
00: 1012 0000
BP: 2000 00C0 [0001]
EC: 0000 0000 [3000]
T0: 0000 00E8 [010F]
System halt!
All generate image headers also differ from the ones generated by
bromimage, however, for SPI-NAND and eMMC they still work.
hexdiff of SD card bl2.img
@@ -65,7 +65,7 @@
00004420 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
*
00004600 42 52 4c 59 54 00 00 00 01 00 00 00 00 4a 00 00 |BRLYT........J..|
-00004610 88 51 03 00 42 42 42 42 08 00 01 00 00 06 00 00 |.Q..BBBB........|
+00004610 88 51 03 00 42 42 42 42 08 00 01 00 00 4a 00 00 |.Q..BBBB.....J..|
00004620 88 51 03 00 ff ff ff ff ff ff ff ff ff ff ff ff |.Q..............|
00004630 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
*
@@ -73,15 +73,15 @@
00004a10 4f 00 00 00 01 00 00 00 01 00 05 01 00 0d 20 00 |O............. .|
00004a20 88 07 03 00 88 0d 03 00 00 03 00 00 20 00 00 00 |............ ...|
00004a30 00 03 00 00 01 00 00 00 4d 4d 4d 01 0c 00 01 00 |........MMM.....|
-00004a40 01 00 00 00 4d 4d 4d 01 14 00 02 00 00 00 00 00 |....MMM.........|
-00004a50 10 00 00 00 80 00 00 00 4d 4d 4d 01 14 02 03 00 |........MMM.....|
-00004a60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
-*
-00004c60 00 00 00 00 00 00 00 00 00 00 00 00 4d 4d 4d 03 |............MMM.|
-00004c70 64 00 07 00 90 11 00 00 00 00 00 00 00 00 00 00 |d...............|
-00004c80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+00004a40 01 00 00 00 4d 4d 4d 03 64 00 07 00 90 11 00 00 |....MMM.d.......|
+00004a50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
*
-00004cc0 00 64 00 00 88 13 00 00 00 00 00 00 00 00 00 00 |.d..............|
+00004a90 00 00 00 00 00 00 00 00 00 64 00 00 88 13 00 00 |.........d......|
+00004aa0 00 00 00 00 00 00 00 00 4d 4d 4d 01 14 02 03 00 |........MMM.....|
+00004ab0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+*
+00004cb0 00 00 00 00 00 00 00 00 00 00 00 00 4d 4d 4d 01 |............MMM.|
+00004cc0 14 00 02 00 00 00 00 00 10 00 00 00 80 00 00 00 |................|
00004cd0 4d 4d 4d 01 30 00 08 00 03 00 00 00 00 00 00 00 |MMM.0...........|
00004ce0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
*
hexdiff of SPI-NOR bl2.img
@@ -11,15 +11,15 @@
00000610 4f 00 00 00 01 00 00 00 01 00 05 01 00 0d 20 00 |O............. .|
00000620 70 0a 03 00 70 10 03 00 00 03 00 00 20 00 00 00 |p...p....... ...|
00000630 00 03 00 00 01 00 00 00 4d 4d 4d 01 0c 00 01 00 |........MMM.....|
-00000640 01 00 00 00 4d 4d 4d 03 64 00 07 00 90 11 00 00 |....MMM.d.......|
-00000650 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+00000640 01 00 00 00 4d 4d 4d 01 14 00 02 00 00 00 00 00 |....MMM.........|
+00000650 10 00 00 00 80 00 00 00 4d 4d 4d 01 14 02 03 00 |........MMM.....|
+00000660 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
*
-00000690 00 00 00 00 00 00 00 00 00 64 00 00 88 13 00 00 |.........d......|
-000006a0 00 00 00 00 00 00 00 00 4d 4d 4d 01 14 02 03 00 |........MMM.....|
-000006b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
+00000860 00 00 00 00 00 00 00 00 00 00 00 00 4d 4d 4d 03 |............MMM.|
+00000870 64 00 07 00 90 11 00 00 00 00 00 00 00 00 00 00 |d...............|
+00000880 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
*
-000008b0 00 00 00 00 00 00 00 00 00 00 00 00 4d 4d 4d 01 |............MMM.|
-000008c0 14 00 02 00 00 00 00 00 10 00 00 00 80 00 00 00 |................|
+000008c0 00 64 00 00 88 13 00 00 00 00 00 00 00 00 00 00 |.d..............|
000008d0 4d 4d 4d 01 30 00 08 00 03 00 00 00 00 00 00 00 |MMM.0...........|
000008e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
*
I'll try to have a look at this more deepply in the next days, but if
you already spot the error I'd also be glad ;)
Cheers
Daniel
[1]: https://github.com/dangowrt/arm-trusted-firmware/commit/3b8a17bd847d864379fe9953a82991b522f64add
On Fri, Aug 05, 2022 at 04:43:39PM +0800, Weijie Gao wrote:
> Hi Daniel,
>
> It turns out that this was caused by a setting change of company's mail
> gateway.
> I'll send v2 later.
>
> Best Regards,
>
> Weijie
>
> On Thu, 2022-08-04 at 16:50 +0800, Weijie Gao wrote:
> > Hi Daniel,
> >
> > Thanks for the reminder.
> > I found more errornous line-breaks in other patches...
> > I'll find a way to fix that.
> >
> > Best Regards,
> > Weijie
> >
> > On Thu, 2022-08-04 at 10:37 +0200, Daniel Golle wrote:
> > > Hi Weijie,
> > >
> > > happy to see this series posted!
> > > Trying to apply it unfortunately fails due to errornous line-
> > > breaks,
> > > supposedly inserted by your MUA, see below.
> > >
> > > I didn't go beyond the first patch and it'd be nice if you report
> > > the
> > > whole series without the wrong line-breaks.
> > >
> > > Cheers
> > >
> > >
> > > Daniel
> > >
> > >
> > > On Thu, Aug 04, 2022 at 11:34:28AM +0800, Weijie Gao wrote:
> > > > This patch adds basic support for MediaTek MT7986 SoC.
> > > > This include the file that will initialize the SoC after boot and
> > > > its
> > > > device tree.
> > > >
> > > > Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> > > > ---
> > > > arch/arm/dts/mt7986-u-boot.dtsi | 33 ++
> > > > arch/arm/dts/mt7986.dtsi | 341
> > > > ++++++++++++++++++
> > > > arch/arm/mach-mediatek/Kconfig | 11 +
> > > > arch/arm/mach-mediatek/Makefile | 1 +
> > > > arch/arm/mach-mediatek/mt7986/Makefile | 4 +
> > > > arch/arm/mach-mediatek/mt7986/init.c | 53 +++
> > > > arch/arm/mach-mediatek/mt7986/lowlevel_init.S | 30 ++
> > > > 7 files changed, 473 insertions(+)
> > > > create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi
> > > > create mode 100644 arch/arm/dts/mt7986.dtsi
> > > > create mode 100644 arch/arm/mach-mediatek/mt7986/Makefile
> > > > create mode 100644 arch/arm/mach-mediatek/mt7986/init.c
> > > > create mode 100644 arch/arm/mach-mediatek/mt7986/lowlevel_init.S
> > > >
> > > > diff --git a/arch/arm/dts/mt7986-u-boot.dtsi
> > > > b/arch/arm/dts/mt7986-u-boot.dtsi
> > >
> > > The above two lines should be a single line.
> > >
> > > > new file mode 100644
> > > > index 0000000000..95671f8afa
> > > > --- /dev/null
> > > > +++ b/arch/arm/dts/mt7986-u-boot.dtsi
> > > > @@ -0,0 +1,33 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Copyright (c) 2022 MediaTek Inc.
> > > > + * Author: Sam Shih <sam.shih@mediatek.com>
> > > > + */
> > > > +
> > > > +&topckgen {
> > > > + u-boot,dm-pre-reloc;
> > > > +};
> > > > +
> > > > +&pericfg {
> > > > + u-boot,dm-pre-reloc;
> > > > +};
> > > > +
> > > > +&apmixedsys {
> > > > + u-boot,dm-pre-reloc;
> > > > +};
> > > > +
> > > > +&timer0 {
> > > > + u-boot,dm-pre-reloc;
> > > > +};
> > > > +
> > > > +&uart0 {
> > > > + u-boot,dm-pre-reloc;
> > > > +};
> > > > +
> > > > +&snand {
> > > > + u-boot,dm-pre-reloc;
> > > > +};
> > > > +
> > > > +&pinctrl {
> > > > + u-boot,dm-pre-reloc;
> > > > +};
> > > > diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
> > > > new file mode 100644
> > > > index 0000000000..f235bd8b8c
> > > > --- /dev/null
> > > > +++ b/arch/arm/dts/mt7986.dtsi
> > > > @@ -0,0 +1,341 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Copyright (c) 2022 MediaTek Inc.
> > > > + * Author: Sam Shih <sam.shih@mediatek.com>
> > > > + */
> > > > +
> > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +#include <dt-bindings/phy/phy.h>
> > > > +#include <dt-bindings/clock/mt7986-clk.h>
> > > > +#include <dt-bindings/reset/mt7629-reset.h>
> > > > +#include <dt-bindings/pinctrl/mt65xx.h>
> > > > +
> > > > +/ {
> > > > + compatible = "mediatek,mt7986";
> > > > + interrupt-parent = <&gic>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > +
> > > > + config {
> > > > + u-boot,mmc-env-partition = "u-boot-env";
> > > > + };
> > > > +
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + cpu0: cpu@0 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x0>;
> > > > + };
> > > > + cpu1: cpu@1 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x1>;
> > > > + };
> > > > + cpu2: cpu@2 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x1>;
> > > > + };
> > > > + cpu3: cpu@3 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x1>;
> > > > + };
> > > > + };
> > > > +
> > > > + dummy_clk: dummy12m {
> > > > + compatible = "fixed-clock";
> > > > + clock-frequency = <12000000>;
> > > > + #clock-cells = <0>;
> > > > + /* must need this line, or uart uanable to get
> > > > dummy_clk */
> > > > + u-boot,dm-pre-reloc;
> > > > + };
> > > > +
> > > > + timer {
> > > > + compatible = "arm,armv8-timer";
> > > > + interrupt-parent = <&gic>;
> > > > + clock-frequency = <13000000>;
> > > > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > > > + arm,cpu-registers-not-fw-configured;
> > > > + };
> > > > +
> > > > + timer0: timer@10008000 {
> > > > + compatible = "mediatek,mt7986-timer";
> > > > + reg = <0x10008000 0x1000>;
> > > > + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&infracfg CK_INFRA_CK_F26M>;
> > > > + clock-names = "gpt-clk";
> > > > + u-boot,dm-pre-reloc;
> > > > + };
> > > > +
> > > > + watchdog: watchdog@1001c000 {
> > > > + compatible = "mediatek,mt7986-wdt";
> > > > + reg = <0x1001c000 0x1000>;
> > > > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> > > > + #reset-cells = <1>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + gic: interrupt-controller@c000000 {
> > > > + compatible = "arm,gic-v3";
> > > > + #interrupt-cells = <3>;
> > > > + interrupt-parent = <&gic>;
> > > > + interrupt-controller;
> > > > + reg = <0x0c000000 0x40000>, /* GICD */
> > > > + <0x0c080000 0x200000>; /* GICR */
> > > > +
> > > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > > > + };
> > > > +
> > > > + fixed_plls: apmixedsys@1001E000 {
> > > > + compatible = "mediatek,mt7986-fixed-plls";
> > > > + reg = <0x1001E000 0x1000>;
> > > > + #clock-cells = <1>;
> > > > + };
> > > > +
> > > > + topckgen: topckgen@1001B000 {
> > > > + compatible = "mediatek,mt7986-topckgen";
> > > > + reg = <0x1001B000 0x1000>;
> > > > + clock-parent = <&fixed_plls>;
> > > > + #clock-cells = <1>;
> > > > + };
> > > > +
> > > > + infracfg_ao: infracfg_ao@10001000 {
> > > > + compatible = "mediatek,mt7986-infracfg_ao";
> > > > + reg = <0x10001000 0x68>;
> > > > + clock-parent = <&infracfg>;
> > > > + #clock-cells = <1>;
> > > > + };
> > > > +
> > > > + infracfg: infracfg@10001040 {
> > > > + compatible = "mediatek,mt7986-infracfg";
> > > > + reg = <0x10001000 0x1000>;
> > > > + clock-parent = <&topckgen>;
> > > > + #clock-cells = <1>;
> > > > + };
> > > > +
> > > > + pinctrl: pinctrl@1001f000 {
> > > > + compatible = "mediatek,mt7986-pinctrl";
> > > > + reg = <0x1001f000 0x1000>,
> > > > + <0x11c30000 0x1000>,
> > > > + <0x11c40000 0x1000>,
> > > > + <0x11e20000 0x1000>,
> > > > + <0x11e30000 0x1000>,
> > > > + <0x11f00000 0x1000>,
> > > > + <0x11f10000 0x1000>,
> > > > + <0x1000b000 0x1000>;
> > > > + reg-names = "gpio_base", "iocfg_rt_base",
> > > > "iocfg_rb_base",
> > > > + "iocfg_lt_base", "iocfg_lb_base",
> > > > "iocfg_tr_base",
> > > > + "iocfg_tl_base", "eint";
> > > > + gpio: gpio-controller {
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + };
> > > > + };
> > > > +
> > > > + pwm: pwm@10048000 {
> > > > + compatible = "mediatek,mt7986-pwm";
> > > > + reg = <0x10048000 0x1000>;
> > > > + #clock-cells = <1>;
> > > > + #pwm-cells = <2>;
> > > > + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&infracfg CK_INFRA_PWM>,
> > > > + <&infracfg_ao CK_INFRA_PWM_BSEL>,
> > > > + <&infracfg_ao CK_INFRA_PWM1_CK>,
> > > > + <&infracfg_ao CK_INFRA_PWM2_CK>;
> > > > + assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
> > > > + <&infracfg CK_INFRA_PWM_BSEL>,
> > > > + <&infracfg CK_INFRA_PWM1_SEL>,
> > > > + <&infracfg CK_INFRA_PWM2_SEL>;
> > > > + assigned-clock-parents = <&topckgen
> > > > CK_TOP_CB_M_D4>,
> > > > + <&infracfg
> > > > CK_INFRA_PWM>,
> > > > + <&infracfg
> > > > CK_INFRA_PWM>,
> > > > + <&infracfg
> > > > CK_INFRA_PWM>;
> > > > + clock-names = "top", "main", "pwm1", "pwm2";
> > > > + status = "disabled";
> > > > + u-boot,dm-pre-reloc;
> > > > + };
> > > > +
> > > > + uart0: serial@11002000 {
> > > > + compatible = "mediatek,hsuart";
> > > > + reg = <0x11002000 0x400>;
> > > > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
> > > > + assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
> > > > + <&infracfg_ao
> > > > CK_INFRA_UART0_SEL>;
> > > > + assigned-clock-parents = <&topckgen
> > > > CK_TOP_CB_CKSQ_40M>,
> > > > + <&infracfg
> > > > CK_INFRA_UART>;
> > > > + mediatek,force-highspeed;
> > > > + status = "disabled";
> > > > + u-boot,dm-pre-reloc;
> > > > + };
> > > > +
> > > > + uart1: serial@11003000 {
> > > > + compatible = "mediatek,hsuart";
> > > > + reg = <0x11003000 0x400>;
> > > > + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
> > > > + assigned-clocks = <&infracfg
> > > > CK_INFRA_UART1_SEL>;
> > > > + assigned-clock-parents = <&infracfg
> > > > CK_INFRA_CK_F26M>;
> > > > + mediatek,force-highspeed;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart2: serial@11004000 {
> > > > + compatible = "mediatek,hsuart";
> > > > + reg = <0x11004000 0x400>;
> > > > + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
> > > > + assigned-clocks = <&infracfg
> > > > CK_INFRA_UART2_SEL>;
> > > > + assigned-clock-parents = <&infracfg
> > > > CK_INFRA_CK_F26M>;
> > > > + mediatek,force-highspeed;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + snand: snand@11005000 {
> > > > + compatible = "mediatek,mt7986-snand";
> > > > + reg = <0x11005000 0x1000>,
> > > > + <0x11006000 0x1000>;
> > > > + reg-names = "nfi", "ecc";
> > > > + clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
> > > > + <&infracfg_ao CK_INFRA_NFI1_CK>,
> > > > + <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
> > > > + clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
> > > > + assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
> > > > + <&topckgen CK_TOP_NFI1X_SEL>;
> > > > + assigned-clock-parents = <&topckgen
> > > > CK_TOP_CB_M_D8>,
> > > > + <&topckgen
> > > > CK_TOP_CB_M_D8>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + ethsys: syscon@15000000 {
> > > > + compatible = "mediatek,mt7986-ethsys", "syscon";
> > > > + reg = <0x15000000 0x1000>;
> > > > + clock-parent = <&topckgen>;
> > > > + #clock-cells = <1>;
> > > > + #reset-cells = <1>;
> > > > + };
> > > > +
> > > > + eth: ethernet@15100000 {
> > > > + compatible = "mediatek,mt7986-eth", "syscon";
> > > > + reg = <0x15100000 0x20000>;
> > > > + resets = <ðsys ETHSYS_FE_RST>;
> > > > + reset-names = "fe";
> > > > + mediatek,ethsys = <ðsys>;
> > > > + mediatek,sgmiisys = <&sgmiisys0>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + sgmiisys0: syscon@10060000 {
> > > > + compatible = "mediatek,mt7986-sgmiisys",
> > > > "syscon";
> > > > + reg = <0x10060000 0x1000>;
> > > > + #clock-cells = <1>;
> > > > + };
> > > > +
> > > > + sgmiisys1: syscon@10070000 {
> > > > + compatible = "mediatek,mt7986-sgmiisys",
> > > > "syscon";
> > > > + reg = <0x10070000 0x1000>;
> > > > + #clock-cells = <1>;
> > > > + };
> > > > +
> > > > + spi0: spi@1100a000 {
> > > > + compatible = "mediatek,ipm-spi";
> > > > + reg = <0x1100a000 0x100>;
> > > > + clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
> > > > + <&topckgen CK_TOP_SPI_SEL>;
> > > > + assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
> > > > + <&infracfg CK_INFRA_SPI0_SEL>;
> > > > + assigned-clock-parents = <&topckgen
> > > > CK_TOP_CB_M_D2>,
> > > > + <&topckgen
> > > > CK_INFRA_ISPI0>;
> > > > + clock-names = "sel-clk", "spi-clk";
> > > > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + spi1: spi@1100b000 {
> > > > + compatible = "mediatek,ipm-spi";
> > > > + reg = <0x1100b000 0x100>;
> > > > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + mmc0: mmc@11230000 {
> > > > + compatible = "mediatek,mt7986-mmc";
> > > > + reg = <0x11230000 0x1000>,
> > > > + <0x11C20000 0x1000>;
> > > > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&topckgen CK_TOP_EMMC_416M>,
> > > > + <&topckgen CK_TOP_EMMC_250M>,
> > > > + <&infracfg_ao CK_INFRA_MSDC_CK>;
> > > > + assigned-clocks = <&topckgen
> > > > CK_TOP_EMMC_416M_SEL>,
> > > > + <&topckgen
> > > > CK_TOP_EMMC_250M_SEL>;
> > > > + assigned-clock-parents = <&topckgen
> > > > CK_TOP_CB_M_416M>,
> > > > + <&topckgen
> > > > CK_TOP_NET1_D5_D2>;
> > > > + clock-names = "source", "hclk", "source_cg";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + xhci: xhci@11200000 {
> > > > + compatible = "mediatek,mt7986-xhci",
> > > > + "mediatek,mtk-xhci";
> > > > + reg = <0x11200000 0x2e00>,
> > > > + <0x11203e00 0x0100>;
> > > > + reg-names = "mac", "ippc";
> > > > + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> > > > + phys = <&u2port0 PHY_TYPE_USB2>,
> > > > + <&u3port0 PHY_TYPE_USB3>,
> > > > + <&u2port1 PHY_TYPE_USB2>;
> > > > + clocks = <&dummy_clk>,
> > > > + <&dummy_clk>,
> > > > + <&dummy_clk>,
> > > > + <&dummy_clk>,
> > > > + <&dummy_clk>;
> > > > + clock-names = "sys_ck",
> > > > + "xhci_ck",
> > > > + "ref_ck",
> > > > + "mcu_ck",
> > > > + "dma_ck";
> > > > + tpl-support;
> > > > + status = "okay";
> > > > + };
> > > > +
> > > > + usbtphy: usb-phy@11e10000 {
> > > > + compatible = "mediatek,mt7986",
> > > > + "mediatek,generic-tphy-v2";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + status = "okay";
> > > > +
> > > > + u2port0: usb-phy@11e10000 {
> > > > + reg = <0x11e10000 0x700>;
> > > > + clocks = <&dummy_clk>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + status = "okay";
> > > > + };
> > > > +
> > > > + u3port0: usb-phy@11e10700 {
> > > > + reg = <0x11e10700 0x900>;
> > > > + clocks = <&dummy_clk>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + status = "okay";
> > > > + };
> > > > +
> > > > + u2port1: usb-phy@11e11000 {
> > > > + reg = <0x11e11000 0x700>;
> > > > + clocks = <&dummy_clk>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + status = "okay";
> > > > + };
> > > > + };
> > > > +};
> > > > diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-
> > > > mediatek/Kconfig
> > > > index f79a5c62cd..e059a013db 100644
> > > > --- a/arch/arm/mach-mediatek/Kconfig
> > > > +++ b/arch/arm/mach-mediatek/Kconfig
> > > > @@ -40,6 +40,14 @@ config TARGET_MT7629
> > > > including DDR3, crypto engine, 3x3 11n/ac Wi-Fi,
> > > > Gigabit
> > > > Ethernet,
> > > > switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
> > > >
> > > > +config TARGET_MT7986
> > > > + bool "MediaTek MT7986 SoC"
> > > > + select ARM64
> > > > + help
> > > > + The MediaTek MT7986 is a ARM64-based SoC with a quad-
> > > > core Cortex-A53.
> > > > + including UART, SPI, SPI flash, USB3.0, MMC, NAND,
> > > > SNFI,
> > > > PWM, PCIe,
> > > > + Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
> > > > +
> > > > config TARGET_MT8183
> > > > bool "MediaTek MT8183 SoC"
> > > > select ARM64
> > > > @@ -84,6 +92,7 @@ config SYS_BOARD
> > > > default "mt7622" if TARGET_MT7622
> > > > default "mt7623" if TARGET_MT7623
> > > > default "mt7629" if TARGET_MT7629
> > > > + default "mt7986" if TARGET_MT7986
> > > > default "mt8183" if TARGET_MT8183
> > > > default "mt8512" if TARGET_MT8512
> > > > default "mt8516" if TARGET_MT8516
> > > > @@ -99,6 +108,7 @@ config SYS_CONFIG_NAME
> > > > default "mt7622" if TARGET_MT7622
> > > > default "mt7623" if TARGET_MT7623
> > > > default "mt7629" if TARGET_MT7629
> > > > + default "mt7986" if TARGET_MT7986
> > > > default "mt8183" if TARGET_MT8183
> > > > default "mt8512" if TARGET_MT8512
> > > > default "mt8516" if TARGET_MT8516
> > > > @@ -113,6 +123,7 @@ config MTK_BROM_HEADER_INFO
> > > > string
> > > > default "media=nor" if TARGET_MT8518 || TARGET_MT8512 ||
> > > > TARGET_MT7629 ||
> > > > TARGET_MT7622
> > >
> > > Same here.
> > >
> > > > default "media=emmc" if TARGET_MT8516 || TARGET_MT8365
> > > > ||
> > > > TARGET_MT8183
> > > > + default "media=snand;nandinfo=2k+64" if TARGET_MT7986
> > > > default "lk=1" if TARGET_MT7623
> > > >
> > > > endif
> > > > diff --git a/arch/arm/mach-mediatek/Makefile
> > > > b/arch/arm/mach-mediatek/Makefile
> > >
> > > And here.
> > >
> > > > index 0f5b0c16d2..fe5c3a837c 100644
> > > > --- a/arch/arm/mach-mediatek/Makefile
> > > > +++ b/arch/arm/mach-mediatek/Makefile
> > > > @@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/
> > > > obj-$(CONFIG_TARGET_MT7622) += mt7622/
> > > > obj-$(CONFIG_TARGET_MT7623) += mt7623/
> > > > obj-$(CONFIG_TARGET_MT7629) += mt7629/
> > > > +obj-$(CONFIG_TARGET_MT7986) += mt7986/
> > > > obj-$(CONFIG_TARGET_MT8183) += mt8183/
> > > > obj-$(CONFIG_TARGET_MT8516) += mt8516/
> > > > obj-$(CONFIG_TARGET_MT8518) += mt8518/
> > > > diff --git a/arch/arm/mach-mediatek/mt7986/Makefile
> > > > b/arch/arm/mach-mediatek/mt7986/Makefile
> > >
> > > And here.
> > >
> > > > new file mode 100644
> > > > index 0000000000..007eb4a367
> > > > --- /dev/null
> > > > +++ b/arch/arm/mach-mediatek/mt7986/Makefile
> > > > @@ -0,0 +1,4 @@
> > > > +# SPDX-License-Identifier: GPL-2.0
> > > > +
> > > > +obj-y += init.o
> > > > +obj-y += lowlevel_init.o
> > > > diff --git a/arch/arm/mach-mediatek/mt7986/init.c
> > > > b/arch/arm/mach-mediatek/mt7986/init.c
> > >
> > > And here again.
> > >
> > > > new file mode 100644
> > > > index 0000000000..4884cbdc67
> > > > --- /dev/null
> > > > +++ b/arch/arm/mach-mediatek/mt7986/init.c
> > > > @@ -0,0 +1,53 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Copyright (C) 2022 MediaTek Inc.
> > > > + * Author: Sam Shih <sam.shih@mediatek.com>
> > > > + */
> > > > +
> > > > +#include <fdtdec.h>
> > > > +#include <asm/armv8/mmu.h>
> > > > +#include <init.h>
> > > > +#include <asm/system.h>
> > > > +#include <asm/global_data.h>
> > > > +#include <linux/sizes.h>
> > > > +
> > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > +
> > > > +int print_cpuinfo(void)
> > > > +{
> > > > + printf("CPU: MediaTek MT7986\n");
> > > > + return 0;
> > > > +}
> > > > +
> > > > +int dram_init(void)
> > > > +{
> > > > + gd->ram_size = get_ram_size((void
> > > > *)CONFIG_SYS_SDRAM_BASE,
> > > > SZ_2G);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +void reset_cpu(ulong addr)
> > > > +{
> > > > + psci_system_reset();
> > > > +}
> > > > +
> > > > +static struct mm_region mt7986_mem_map[] = {
> > > > + {
> > > > + /* DDR */
> > > > + .virt = 0x40000000UL,
> > > > + .phys = 0x40000000UL,
> > > > + .size = 0x80000000UL,
> > > > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> > > > PTE_BLOCK_OUTER_SHARE,
> > > > + }, {
> > > > + .virt = 0x00000000UL,
> > > > + .phys = 0x00000000UL,
> > > > + .size = 0x40000000UL,
> > > > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> > > > + PTE_BLOCK_NON_SHARE |
> > > > + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> > > > + }, {
> > > > + 0,
> > > > + }
> > > > +};
> > > > +
> > > > +struct mm_region *mem_map = mt7986_mem_map;
> > > > diff --git a/arch/arm/mach-mediatek/mt7986/lowlevel_init.S
> > > > b/arch/arm/mach-mediatek/mt7986/lowlevel_init.S
> > >
> > > And here.
> > >
> > > > new file mode 100644
> > > > index 0000000000..244d2c1385
> > > > --- /dev/null
> > > > +++ b/arch/arm/mach-mediatek/mt7986/lowlevel_init.S
> > > > @@ -0,0 +1,30 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > > +/*
> > > > + * Copyright (C) 2022 MediaTek Inc.
> > > > + * Author: Sam Shih <sam.shih@mediatek.com>
> > > > + */
> > > > +
> > > > +/*
> > > > + * Switch from AArch64 EL2 to AArch32 EL2
> > > > + * @param inputs:
> > > > + * x0: argument, zero
> > > > + * x1: machine nr
> > > > + * x2: fdt address
> > > > + * x3: input argument
> > > > + * x4: kernel entry point
> > > > + * @param outputs for secure firmware:
> > > > + * x0: function id
> > > > + * x1: kernel entry point
> > > > + * x2: machine nr
> > > > + * x3: fdt address
> > > > +*/
> > > > +
> > > > +.global armv8_el2_to_aarch32
> > > > +armv8_el2_to_aarch32:
> > > > + mov x3, x2
> > > > + mov x2, x1
> > > > + mov x1, x4
> > > > + mov x4, #0
> > > > + ldr x0, =0x82000200
> > > > + SMC #0
> > > > + ret
> > > > --
> > > > 2.17.1
> > > >
next prev parent reply other threads:[~2022-08-06 16:11 UTC|newest]
Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-04 3:34 [PATCH 00/31] Add support for MediaTek MT7981/MT7986 SoCs Weijie Gao
2022-08-04 3:34 ` [PATCH 01/31] arm: mediatek: add support for MediaTek MT7986 SoC Weijie Gao
2022-08-04 8:37 ` Daniel Golle
2022-08-04 8:50 ` Weijie Gao
2022-08-05 8:43 ` Weijie Gao
2022-08-06 16:09 ` Daniel Golle [this message]
2022-08-08 1:37 ` Weijie Gao
2022-08-04 3:34 ` [PATCH 02/31] arm: mediatek: add support for MediaTek MT7981 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 2:17 ` Weijie Gao
2022-08-08 19:26 ` Simon Glass
2022-08-04 3:35 ` [PATCH 03/31] board: mediatek: add MT7986 reference boards Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-09 9:10 ` Daniel Golle
2022-08-12 11:02 ` Weijie Gao
2022-08-12 11:29 ` Daniel Golle
2022-08-04 3:35 ` [PATCH 04/31] board: mediatek: add MT7981 " Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 05/31] mmc: mediatek: add support for MediaTek MT7891/MT7986 SoCs Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 2:22 ` Weijie Gao
2022-08-11 5:50 ` jh80.chung
2022-08-04 3:35 ` [PATCH 06/31] net: mediatek: use a struct to cover variations of all SoCs Weijie Gao
2022-08-04 13:56 ` Simon Glass
2022-08-08 2:28 ` Weijie Gao
2022-08-04 3:35 ` [PATCH 07/31] net: mediatek: stop using bitfileds for DMA descriptors Weijie Gao
2022-08-04 13:56 ` Simon Glass
2022-08-06 17:50 ` Ramon Fried
2022-08-08 2:29 ` Weijie Gao
2022-08-04 3:35 ` [PATCH 08/31] net: mediatek: add support for PDMA v2 Weijie Gao
2022-08-04 13:56 ` Simon Glass
2022-08-06 17:49 ` Ramon Fried
2022-08-04 3:35 ` [PATCH 09/31] net: mediatek: add support for MediaTek MT7981/MT7986 Weijie Gao
2022-08-06 17:48 ` Ramon Fried
2022-08-04 3:35 ` [PATCH 10/31] serial: mtk: add support for using dynamic baud clock souce Weijie Gao
2022-08-04 13:56 ` Simon Glass
2022-08-08 2:36 ` Weijie Gao
2022-08-08 19:26 ` Simon Glass
2022-08-04 3:35 ` [PATCH 11/31] arm: dts: mt7622: force high-speed mode for uart Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 12/31] pwm: mtk: add support for MediaTek MT7986 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 13/31] pwm: mtk: add support for MediaTek MT7981 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 14/31] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:35 ` [PATCH 15/31] watchdog: mediatek: add support for MediaTek MT7986 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 16/31] spi: add support for MediaTek spi-mem controller Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 17/31] i2c: add support for MediaTek I2C interface Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:00 ` Weijie Gao
2022-08-10 11:12 ` Heiko Schocher
2022-08-10 11:24 ` Michael Nazzareno Trimarchi
2022-08-12 9:46 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 18/31] arm: dts: mt7622: add i2c support Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 19/31] dt-bindings: pinctrl: mediatek: add a header for common pinconf parameters Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 20/31] pinctrl: mediatek: add pinctrl driver for MT7981 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 21/31] pinctrl: mediatek: add pinctrl driver for MT7986 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 22/31] clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:01 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 23/31] clk: mediatek: add support to configure clock driver parent Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-13 4:18 ` Sean Anderson
2022-08-23 10:43 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 24/31] clk: mediatek: add infrasys clock mux support Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-13 4:21 ` Sean Anderson
2022-08-17 8:00 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:10 ` Weijie Gao
2022-08-13 4:25 ` Sean Anderson
2022-08-17 8:08 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 26/31] clk: mediatek: add clock driver support for MediaTek MT7986 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:13 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 27/31] clk: mediatek: add clock driver support for MediaTek MT7981 SoC Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:18 ` Weijie Gao
2022-08-13 4:31 ` Sean Anderson
2022-08-17 8:16 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 28/31] tools: mtk_image: split gfh header verification into a new function Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-04 3:36 ` [PATCH 29/31] tools: mtk_image: split the code of generating NAND header into a new file Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:23 ` Weijie Gao
2022-08-05 18:26 ` Daniel Golle
2022-08-08 3:26 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 30/31] tools: mtk_image: add support for nand headers used by newer chips Weijie Gao
2022-08-04 13:57 ` Simon Glass
2022-08-08 3:31 ` Weijie Gao
2022-08-04 3:36 ` [PATCH 31/31] MAINTAINERS: update maintainer for MediaTek ARM platform Weijie Gao
2022-08-04 13:57 ` Simon Glass
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Yu6SVnCZe4ZkJbCa@makrotopia.org \
--to=daniel@makrotopia.org \
--cc=GSS_MTK_Uboot_upstream@mediatek.com \
--cc=u-boot@lists.denx.de \
--cc=weijie.gao@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.