From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0FB0C00140 for ; Tue, 26 Jul 2022 15:16:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HrVzYTlzQmLlENWnUsUS0WoFwKpshNcfnsrX1IfT+Q4=; b=Rrk7pOSsfUHeno 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+0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06B62C433C1; Tue, 26 Jul 2022 15:15:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1658848536; bh=JdYLPvm15DCGWDloUpXmxYYLmSi+V/FEw3vBEoaF+Jw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=xBokB72rddFLxtHSosxuv3alJqsdn0oyulNn4jSAaE2unHKS0UIM1wLxL2J8T16L0 k39NRaycdo4vXVxUP4FOVG+nE53iMehPLaex58j9lRVfL0OQ2uKPiGgF5dJfnEg16i sBHsTSPvke7L3MCKx6Puv+grQDjTJVYq56eH/DFk= Date: Tue, 26 Jul 2022 17:15:30 +0200 From: Greg KH To: yuji2.ishikawa@toshiba.co.jp Cc: robh+dt@kernel.org, hverkuil@xs4all.nl, nobuhiro1.iwamatsu@toshiba.co.jp, corbet@lwn.net, sumit.semwal@linaro.org, christian.koenig@amd.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org Subject: Re: [PATCH v2 3/5] soc: visconti: Add Toshiba Visconti DNN image processing accelerator Message-ID: References: <20220722082858.17880-1-yuji2.ishikawa@toshiba.co.jp> <20220722082858.17880-4-yuji2.ishikawa@toshiba.co.jp> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220726_081539_408838_E1EDB63D X-CRM114-Status: GOOD ( 34.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVHVlLCBKdWwgMjYsIDIwMjIgYXQgMDY6MTA6MzdBTSArMDAwMCwgeXVqaTIuaXNoaWthd2FA dG9zaGliYS5jby5qcCB3cm90ZToKPiBIaSBHcmVnCj4gCj4gVGhhbmsgeW91IGZvciB5b3VyIGNv bW1lbnRzLgo+IAo+ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0KPiA+IEZyb206IEdyZWcg S0ggPGdyZWdraEBsaW51eGZvdW5kYXRpb24ub3JnPgo+ID4gU2VudDogTW9uZGF5LCBKdWx5IDI1 LCAyMDIyIDk6NTEgUE0KPiA+IFRvOiBpc2hpa2F3YSB5dWppKOefs+W3nSDmgqDlj7gg4peL77yy 77yk77yj4pah77yh77yp77y077yj4peL77yl77yh6ZaLKQo+ID4gPHl1amkyLmlzaGlrYXdhQHRv c2hpYmEuY28uanA+Cj4gPiBDYzogUm9iIEhlcnJpbmcgPHJvYmgrZHRAa2VybmVsLm9yZz47IEhh bnMgVmVya3VpbCA8aHZlcmt1aWxAeHM0YWxsLm5sPjsKPiA+IGl3YW1hdHN1IG5vYnVoaXJvKOWy qeadviDkv6HmtIsg4pah77yz77y377yj4pev77yh77yj77y0KQo+ID4gPG5vYnVoaXJvMS5pd2Ft YXRzdUB0b3NoaWJhLmNvLmpwPjsgSm9uYXRoYW4gQ29yYmV0IDxjb3JiZXRAbHduLm5ldD47Cj4g PiBTdW1pdCBTZW13YWwgPHN1bWl0LnNlbXdhbEBsaW5hcm8ub3JnPjsgQ2hyaXN0aWFuIEvDtm5p Zwo+ID4gPGNocmlzdGlhbi5rb2VuaWdAYW1kLmNvbT47IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMu aW5mcmFkZWFkLm9yZzsKPiA+IGxpbnV4LWtlcm5lbEB2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LW1l ZGlhQHZnZXIua2VybmVsLm9yZzsKPiA+IGRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmc7 IGxpbmFyby1tbS1zaWdAbGlzdHMubGluYXJvLm9yZwo+ID4gU3ViamVjdDogUmU6IFtQQVRDSCB2 MiAzLzVdIHNvYzogdmlzY29udGk6IEFkZCBUb3NoaWJhIFZpc2NvbnRpIEROTiBpbWFnZQo+ID4g cHJvY2Vzc2luZyBhY2NlbGVyYXRvcgo+ID4gCj4gPiBPbiBGcmksIEp1bCAyMiwgMjAyMiBhdCAw NToyODo1NlBNICswOTAwLCBZdWppIElzaGlrYXdhIHdyb3RlOgo+ID4gPiAtLS0gL2Rldi9udWxs Cj4gPiA+ICsrKyBiL2RyaXZlcnMvc29jL3Zpc2NvbnRpL3VhcGkvZG5uLmgKPiA+ID4gQEAgLTAs MCArMSw3NyBAQAo+ID4gPiArLyogU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAgV0lU SCBMaW51eC1zeXNjYWxsLW5vdGUgKi8KPiA+ID4gKy8qIFRvc2hpYmEgVmlzY29udGkgRE5OIEFj Y2VsZXJhdG9yIFN1cHBvcnQKPiA+ID4gKyAqCj4gPiA+ICsgKiAoQykgQ29weXJpZ2h0IDIwMjIg VE9TSElCQSBDT1JQT1JBVElPTgo+ID4gPiArICogKEMpIENvcHlyaWdodCAyMDIyIFRvc2hpYmEg RWxlY3Ryb25pYyBEZXZpY2VzICYgU3RvcmFnZQo+ID4gPiArQ29ycG9yYXRpb24gICovCj4gPiA+ ICsKPiA+ID4gKyNpZm5kZWYgX1VBUElfTElOVVhfRE5OX0gKPiA+ID4gKyNkZWZpbmUgX1VBUElf TElOVVhfRE5OX0gKPiA+ID4gKwo+ID4gPiArI2luY2x1ZGUgPGxpbnV4L2lvY3RsLmg+Cj4gPiA+ ICsjaW5jbHVkZSA8bGludXgvdHlwZXMuaD4KPiA+ID4gKyNpbmNsdWRlICJpcGEuaCIKPiA+ID4g Kwo+ID4gPiArI2RlZmluZSBEUlZfRE5OX0JJVF9DT05GSUdfREVTQ19GSU5BTCAoMHg4MDAwVSkK PiA+ID4gKyNkZWZpbmUgRFJWX0ROTl9CVUZGRVJfSU5ERVhfTUFYICAgICAgKDE1KQo+ID4gPiAr Cj4gPiA+ICsjZGVmaW5lIERSVl9ETk5fQkFTRV9BRERSX05VTSAoOFUpIC8qIEROTiBudW1iZXIg b2YgYmFzZQo+ID4gYWRkcmVzcyAqLwo+ID4gPiArCj4gPiA+ICsjZGVmaW5lIERSVl9ETk5fQkFT RV9BRERSX1BVUlBPU0VfSU5QVVQJICAgICgxVSkKPiA+ID4gKyNkZWZpbmUgRFJWX0ROTl9CQVNF X0FERFJfUFVSUE9TRV9PVVRQVVQgICAgKDJVKQo+ID4gPiArI2RlZmluZSBEUlZfRE5OX0JBU0Vf QUREUl9QVVJQT1NFX0FXQgkgICAgKDNVKQo+ID4gPiArI2RlZmluZSBEUlZfRE5OX0JBU0VfQURE Ul9QVVJQT1NFX1RFTVBPUkFSWSAoNFUpCj4gPiA+ICsKPiA+ID4gKy8qKgo+ID4gPiArICogc3Ry dWN0IGRydl9kbm5fc3RhdHVzIC0gRE5OIElQQSBzdGF0dXMgZm9yIElPQ19JUEFfR0VUX1NUQVRV Uwo+ID4gPiArICoKPiA+ID4gKyAqIEBzdGF0ZTogICAgIFN0YXRlIG9mIGRyaXZlcgo+ID4gPiAr ICogQGVlcl9jbWQ6ICAgRXhlY3V0aW9uIGVycm9yIGNvbW1hbmQKPiA+ID4gKyAqIEBlZXI6ICAg ICAgIEV4ZWN1dGlvbiBlcnJvcgo+ID4gPiArICogQHJlc2VydmVkOiAgUGFkZGluZwo+ID4gPiAr ICogQGVlcl9mbGFnczogRXhlY3V0aW9uIGVycm9yIGZsYWdzCj4gPiA+ICsgKi8KPiA+ID4gK3N0 cnVjdCBkcnZfZG5uX3N0YXR1cyB7Cj4gPiA+ICsJZW51bSBkcnZfaXBhX3N0YXRlIHN0YXRlOwo+ ID4gPiArCV9fdTMyIGVlcl9jbWQ7Cj4gPiA+ICsJX191MzIgZWVyIDogMTsKPiA+ID4gKwlfX3Uz MiByZXNlcnZlZCA6IDMxOwo+ID4gCj4gPiBiaXRmaWVsZHMgd2lsbCBub3Qgd29yayBsaWtlIHRo aXMgZm9yIHVhcGkgZmlsZXMsIHNvcnJ5Lgo+IAo+IEknbGwgY2hhbmdlIHRoZSB0eXBlIG9mIHRo ZSBtZW1iZXIgZWVyIGZyb20gYml0ZmllbGQgdG8gYm9vbC4KCmJvb2wgd2lsbCBub3Qgd29yayBm b3IgYSB1c2VyL2tlcm5lbCBhcGkgc3RydWN0dXJlIGF0IGFsbCwgc29ycnkuCgo+ID4gPiArCV9f dTMyIGVlcl9mbGFnc1szMl07Cj4gPiAKPiA+IFdoYXQgZW5kaWFuIGlzIGFsbCBvZiB0aGVzZT8g IEJpZz8gIExpdHRsZT8gIFVua25vd24/Cj4gCj4gVGhlIHByb2Nlc3NvcnMgYW5kIGFjY2VsZXJh dG9ycyBhcmUgbGl0dGxlIGVuZGlhbiBpbiBWaXNjb250aSBTb0MuCj4gRG8gSSBoYXZlIHRvIHVz ZSBtb3JlIHNwZWNpZmljIHR5cGUgc3VjaCBhcyBfX2xlMzIgPwoKT2YgY291cnNlLCB0aGlzIGhh cyB0byBiZSBkZWZpbmVkIGFzIHRvIGhvdyB0aGUgaGFyZHdhcmUgc2VlcyBpdC4gIFdoeQp3b3Vs ZG4ndCB5b3Ugc3BlY2lmeSB0aGlzPwoKPiA+ID4gK307Cj4gPiA+ICsKPiA+ID4gK3N0cnVjdCBk cnZfZG5uX2Jhc2VfYWRkciB7Cj4gPiA+ICsJX191MzIgcHVycG9zZTsKPiA+ID4gKwl1bmlvbiB7 Cj4gPiA+ICsJCXN0cnVjdCBkcnZfaXBhX2FkZHIgaXBhX2FkZHI7Cj4gPiA+ICsJCXVpbnRwdHJf dCBsaXN0X2FkZHI7Cj4gPiAKPiA+IFlvdSByZWFsbHkgZG8gbm90IGV2ZXIgd2FudCBhIHVpbnRw dHJfdCBpbiBhIHVhcGkgZmlsZSwgdGhhdCdzIG5vdCBnb2luZyB0byBiZQo+ID4gcG9ydGFibGUg YXQgYWxsLiAgSXQncyBhbHNvIG5vdCBhIHZhbGlkIGtlcm5lbCB0eXBlIDooCj4gCj4gSSB1bmRl cnN0YW5kLiBUaGUgbWVtYmVyIGxpc3RfYWRkciBzaG91bGQgYmUgdHlwZWQgInN0cnVjdCBkcnZf aXBhX2FkZHIqIi4KCk5vLCBub3QgYXQgYWxsLCB0aGF0IHRvbyB3aWxsIG5vdCB3b3JrIGFuZCBp cyBub3QgcG9ydGFibGUuICBQbGVhc2UgcmVhZAp0aGUgZG9jdW1lbnRhdGlvbiBpbiB0aGUga2Vy bmVsIGZvciBob3cgdG8gd3JpdGUgY29ycmVjdCB1c2VyL2tlcm5lbAphcGlzIHdpdGggaW9jdGwg c3RydWN0dXJlcy4gIEl0IGlzIGFsbCBkb2N1bWVudGVkIHRoZXJlLCBwbGVhc2UgZG8gbm90Cmln bm9yZSBpdCBhbmQgY3JlYXRlIGFuIGFwaSB0aGF0IHdpbGwgYmUgYnJva2VuLgoKPiA+ID4gKyAq IEBjb25maWdfZG9uZTogICAgICAgICAgRmxhZ3Mgb2YgY2FsbGVkIGNvbmZpZ3VyYXRpb24KPiA+ ID4gKyAqIEBidWZmZXJfaW5mbzogICAgICAgICAgVGFibGUgb2YgYnVmZmVyIGluZm9ybWF0aW9u Cj4gPiA+ICsgKiBAYnVmZmVyX2luZm9fbnVtOiAgICAgIE51bWJlciBvZiBidWZmZXJfaW5mbwo+ ID4gPiArICovCj4gPiA+ICtzdHJ1Y3QgZHJ2X2Rubl9kZXNjcmlwdG9yIHsKPiA+ID4gKwlzdHJ1 Y3QgZHJ2X2lwYV9hZGRyIGNvbmZpZ3VyYXRpb247Cj4gPiA+ICsJX191MzIgY29uZmlndXJhdGlv bl9vZmZzZXQ7Cj4gPiAKPiA+IFdoYXQgZW5kaWFuIGFyZSBhbnkgb2YgdGhlc2U/Cj4gCj4gVGhl eSBhcmUgbGl0dGxlIGVuZGlhbiBhcyBwcm9jZXNzb3JzIGFuZCBhY2NlbGVyYXRvcnMgYXJlIExF Lgo+IERvIEkgaGF2ZSB0byB1c2Ugc3BlY2lmaWMgdHlwZSBzdWNoIGFzIF9fbGUzMj8KClllcywg YXMgdGhhdCBpcyBkZWZpbmVkIGJ5IHlvdXIgaGFyZHdhcmUsIG5vdCB0aGUgcHJvY2Vzc29yIHRo ZSBrZXJuZWwKaXMgcnVubmluZyBhcy4KCj4gRG8gd2UgbmVlZCBzcGVjaWFsIGNhcmUgZm9yIGVu ZGlhbm5lc3MJd2hlbiB1c2VybGFuZCBhbmQga2VybmVsIGFyZSBzaGFyaW5nIGRhdGEgKGEgZHJ2 X2Rubl9kZXNjcmlwdG9yIGluc3RhbmNlKSA/CgpZZXMsIHdoeSB3b3VsZG4ndCB5b3U/Cgo+IEkg dGhvdWdodCB0aGVyZSdyZSBubyBlbmRpYW5uZXNzIHByb2JsZW0gd2hlbiB0aGUgZHJpdmVyIGlz IHJlYWRpbmcvd3JpdGluZyBIVydzIDMyYml0IHJlZ2lzdGVycy4KCklzIHRoYXQgd2hhdCB5b3Ug YXJlIGRvaW5nIGhlcmU/ICBJdCdzIGltcG9zc2libGUgdG8gdGVsbC4KCkZvciBkYXRhIHRoYXQg b25seSBjcm9zc2VzIHRoZSB1c2VyL2tlcm5lbCBib3VuZHJ5LCB5b3UgY2FuIHVzZSB0aGUKbmF0 aXZlIHByb2Nlc3NvciBlbmRpYW4sIGJ1dCB3aGVuIGl0IGNyb3NzZXMgdGhlIGtlcm5lbC9oYXJk d2FyZQpib3VuZHJ5LCB5b3UgSEFWRSB0byBzcGVjaWZ5IGl0IGFzIHRvIHdoYXQgdGhlIGhhcmR3 YXJlIGV4cGVjdHMuCgp0aGFua3MsCgpncmVnIGstaAoKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGlu dXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQu b3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9964C00140 for ; Tue, 26 Jul 2022 15:15:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A403C14A203; Tue, 26 Jul 2022 15:15:42 +0000 (UTC) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0F71810F2C3 for ; Tue, 26 Jul 2022 15:15:38 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 33028B80FF0; Tue, 26 Jul 2022 15:15:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06B62C433C1; Tue, 26 Jul 2022 15:15:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1658848536; bh=JdYLPvm15DCGWDloUpXmxYYLmSi+V/FEw3vBEoaF+Jw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=xBokB72rddFLxtHSosxuv3alJqsdn0oyulNn4jSAaE2unHKS0UIM1wLxL2J8T16L0 k39NRaycdo4vXVxUP4FOVG+nE53iMehPLaex58j9lRVfL0OQ2uKPiGgF5dJfnEg16i sBHsTSPvke7L3MCKx6Puv+grQDjTJVYq56eH/DFk= Date: Tue, 26 Jul 2022 17:15:30 +0200 From: Greg KH To: yuji2.ishikawa@toshiba.co.jp Subject: Re: [PATCH v2 3/5] soc: visconti: Add Toshiba Visconti DNN image processing accelerator Message-ID: References: <20220722082858.17880-1-yuji2.ishikawa@toshiba.co.jp> <20220722082858.17880-4-yuji2.ishikawa@toshiba.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linaro-mm-sig@lists.linaro.org, corbet@lwn.net, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, sumit.semwal@linaro.org, hverkuil@xs4all.nl, robh+dt@kernel.org, nobuhiro1.iwamatsu@toshiba.co.jp, christian.koenig@amd.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, Jul 26, 2022 at 06:10:37AM +0000, yuji2.ishikawa@toshiba.co.jp wrote: > Hi Greg > > Thank you for your comments. > > > -----Original Message----- > > From: Greg KH > > Sent: Monday, July 25, 2022 9:51 PM > > To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開) > > > > Cc: Rob Herring ; Hans Verkuil ; > > iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ) > > ; Jonathan Corbet ; > > Sumit Semwal ; Christian König > > ; linux-arm-kernel@lists.infradead.org; > > linux-kernel@vger.kernel.org; linux-media@vger.kernel.org; > > dri-devel@lists.freedesktop.org; linaro-mm-sig@lists.linaro.org > > Subject: Re: [PATCH v2 3/5] soc: visconti: Add Toshiba Visconti DNN image > > processing accelerator > > > > On Fri, Jul 22, 2022 at 05:28:56PM +0900, Yuji Ishikawa wrote: > > > --- /dev/null > > > +++ b/drivers/soc/visconti/uapi/dnn.h > > > @@ -0,0 +1,77 @@ > > > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > > +/* Toshiba Visconti DNN Accelerator Support > > > + * > > > + * (C) Copyright 2022 TOSHIBA CORPORATION > > > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage > > > +Corporation */ > > > + > > > +#ifndef _UAPI_LINUX_DNN_H > > > +#define _UAPI_LINUX_DNN_H > > > + > > > +#include > > > +#include > > > +#include "ipa.h" > > > + > > > +#define DRV_DNN_BIT_CONFIG_DESC_FINAL (0x8000U) > > > +#define DRV_DNN_BUFFER_INDEX_MAX (15) > > > + > > > +#define DRV_DNN_BASE_ADDR_NUM (8U) /* DNN number of base > > address */ > > > + > > > +#define DRV_DNN_BASE_ADDR_PURPOSE_INPUT (1U) > > > +#define DRV_DNN_BASE_ADDR_PURPOSE_OUTPUT (2U) > > > +#define DRV_DNN_BASE_ADDR_PURPOSE_AWB (3U) > > > +#define DRV_DNN_BASE_ADDR_PURPOSE_TEMPORARY (4U) > > > + > > > +/** > > > + * struct drv_dnn_status - DNN IPA status for IOC_IPA_GET_STATUS > > > + * > > > + * @state: State of driver > > > + * @eer_cmd: Execution error command > > > + * @eer: Execution error > > > + * @reserved: Padding > > > + * @eer_flags: Execution error flags > > > + */ > > > +struct drv_dnn_status { > > > + enum drv_ipa_state state; > > > + __u32 eer_cmd; > > > + __u32 eer : 1; > > > + __u32 reserved : 31; > > > > bitfields will not work like this for uapi files, sorry. > > I'll change the type of the member eer from bitfield to bool. bool will not work for a user/kernel api structure at all, sorry. > > > + __u32 eer_flags[32]; > > > > What endian is all of these? Big? Little? Unknown? > > The processors and accelerators are little endian in Visconti SoC. > Do I have to use more specific type such as __le32 ? Of course, this has to be defined as to how the hardware sees it. Why wouldn't you specify this? > > > +}; > > > + > > > +struct drv_dnn_base_addr { > > > + __u32 purpose; > > > + union { > > > + struct drv_ipa_addr ipa_addr; > > > + uintptr_t list_addr; > > > > You really do not ever want a uintptr_t in a uapi file, that's not going to be > > portable at all. It's also not a valid kernel type :( > > I understand. The member list_addr should be typed "struct drv_ipa_addr*". No, not at all, that too will not work and is not portable. Please read the documentation in the kernel for how to write correct user/kernel apis with ioctl structures. It is all documented there, please do not ignore it and create an api that will be broken. > > > + * @config_done: Flags of called configuration > > > + * @buffer_info: Table of buffer information > > > + * @buffer_info_num: Number of buffer_info > > > + */ > > > +struct drv_dnn_descriptor { > > > + struct drv_ipa_addr configuration; > > > + __u32 configuration_offset; > > > > What endian are any of these? > > They are little endian as processors and accelerators are LE. > Do I have to use specific type such as __le32? Yes, as that is defined by your hardware, not the processor the kernel is running as. > Do we need special care for endianness when userland and kernel are sharing data (a drv_dnn_descriptor instance) ? Yes, why wouldn't you? > I thought there're no endianness problem when the driver is reading/writing HW's 32bit registers. Is that what you are doing here? It's impossible to tell. For data that only crosses the user/kernel boundry, you can use the native processor endian, but when it crosses the kernel/hardware boundry, you HAVE to specify it as to what the hardware expects. thanks, greg k-h From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0F03C00140 for ; Tue, 26 Jul 2022 15:15:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233883AbiGZPPj (ORCPT ); Tue, 26 Jul 2022 11:15:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229582AbiGZPPi (ORCPT ); Tue, 26 Jul 2022 11:15:38 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E957317E37; Tue, 26 Jul 2022 08:15:36 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 86EFE6069B; Tue, 26 Jul 2022 15:15:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06B62C433C1; Tue, 26 Jul 2022 15:15:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1658848536; bh=JdYLPvm15DCGWDloUpXmxYYLmSi+V/FEw3vBEoaF+Jw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=xBokB72rddFLxtHSosxuv3alJqsdn0oyulNn4jSAaE2unHKS0UIM1wLxL2J8T16L0 k39NRaycdo4vXVxUP4FOVG+nE53iMehPLaex58j9lRVfL0OQ2uKPiGgF5dJfnEg16i sBHsTSPvke7L3MCKx6Puv+grQDjTJVYq56eH/DFk= Date: Tue, 26 Jul 2022 17:15:30 +0200 From: Greg KH To: yuji2.ishikawa@toshiba.co.jp Cc: robh+dt@kernel.org, hverkuil@xs4all.nl, nobuhiro1.iwamatsu@toshiba.co.jp, corbet@lwn.net, sumit.semwal@linaro.org, christian.koenig@amd.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org Subject: Re: [PATCH v2 3/5] soc: visconti: Add Toshiba Visconti DNN image processing accelerator Message-ID: References: <20220722082858.17880-1-yuji2.ishikawa@toshiba.co.jp> <20220722082858.17880-4-yuji2.ishikawa@toshiba.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org On Tue, Jul 26, 2022 at 06:10:37AM +0000, yuji2.ishikawa@toshiba.co.jp wrote: > Hi Greg > > Thank you for your comments. > > > -----Original Message----- > > From: Greg KH > > Sent: Monday, July 25, 2022 9:51 PM > > To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開) > > > > Cc: Rob Herring ; Hans Verkuil ; > > iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ) > > ; Jonathan Corbet ; > > Sumit Semwal ; Christian König > > ; linux-arm-kernel@lists.infradead.org; > > linux-kernel@vger.kernel.org; linux-media@vger.kernel.org; > > dri-devel@lists.freedesktop.org; linaro-mm-sig@lists.linaro.org > > Subject: Re: [PATCH v2 3/5] soc: visconti: Add Toshiba Visconti DNN image > > processing accelerator > > > > On Fri, Jul 22, 2022 at 05:28:56PM +0900, Yuji Ishikawa wrote: > > > --- /dev/null > > > +++ b/drivers/soc/visconti/uapi/dnn.h > > > @@ -0,0 +1,77 @@ > > > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > > +/* Toshiba Visconti DNN Accelerator Support > > > + * > > > + * (C) Copyright 2022 TOSHIBA CORPORATION > > > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage > > > +Corporation */ > > > + > > > +#ifndef _UAPI_LINUX_DNN_H > > > +#define _UAPI_LINUX_DNN_H > > > + > > > +#include > > > +#include > > > +#include "ipa.h" > > > + > > > +#define DRV_DNN_BIT_CONFIG_DESC_FINAL (0x8000U) > > > +#define DRV_DNN_BUFFER_INDEX_MAX (15) > > > + > > > +#define DRV_DNN_BASE_ADDR_NUM (8U) /* DNN number of base > > address */ > > > + > > > +#define DRV_DNN_BASE_ADDR_PURPOSE_INPUT (1U) > > > +#define DRV_DNN_BASE_ADDR_PURPOSE_OUTPUT (2U) > > > +#define DRV_DNN_BASE_ADDR_PURPOSE_AWB (3U) > > > +#define DRV_DNN_BASE_ADDR_PURPOSE_TEMPORARY (4U) > > > + > > > +/** > > > + * struct drv_dnn_status - DNN IPA status for IOC_IPA_GET_STATUS > > > + * > > > + * @state: State of driver > > > + * @eer_cmd: Execution error command > > > + * @eer: Execution error > > > + * @reserved: Padding > > > + * @eer_flags: Execution error flags > > > + */ > > > +struct drv_dnn_status { > > > + enum drv_ipa_state state; > > > + __u32 eer_cmd; > > > + __u32 eer : 1; > > > + __u32 reserved : 31; > > > > bitfields will not work like this for uapi files, sorry. > > I'll change the type of the member eer from bitfield to bool. bool will not work for a user/kernel api structure at all, sorry. > > > + __u32 eer_flags[32]; > > > > What endian is all of these? Big? Little? Unknown? > > The processors and accelerators are little endian in Visconti SoC. > Do I have to use more specific type such as __le32 ? Of course, this has to be defined as to how the hardware sees it. Why wouldn't you specify this? > > > +}; > > > + > > > +struct drv_dnn_base_addr { > > > + __u32 purpose; > > > + union { > > > + struct drv_ipa_addr ipa_addr; > > > + uintptr_t list_addr; > > > > You really do not ever want a uintptr_t in a uapi file, that's not going to be > > portable at all. It's also not a valid kernel type :( > > I understand. The member list_addr should be typed "struct drv_ipa_addr*". No, not at all, that too will not work and is not portable. Please read the documentation in the kernel for how to write correct user/kernel apis with ioctl structures. It is all documented there, please do not ignore it and create an api that will be broken. > > > + * @config_done: Flags of called configuration > > > + * @buffer_info: Table of buffer information > > > + * @buffer_info_num: Number of buffer_info > > > + */ > > > +struct drv_dnn_descriptor { > > > + struct drv_ipa_addr configuration; > > > + __u32 configuration_offset; > > > > What endian are any of these? > > They are little endian as processors and accelerators are LE. > Do I have to use specific type such as __le32? Yes, as that is defined by your hardware, not the processor the kernel is running as. > Do we need special care for endianness when userland and kernel are sharing data (a drv_dnn_descriptor instance) ? Yes, why wouldn't you? > I thought there're no endianness problem when the driver is reading/writing HW's 32bit registers. Is that what you are doing here? It's impossible to tell. For data that only crosses the user/kernel boundry, you can use the native processor endian, but when it crosses the kernel/hardware boundry, you HAVE to specify it as to what the hardware expects. thanks, greg k-h