From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1FBEC00140 for ; Wed, 10 Aug 2022 15:42:10 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 296424DAD0; Wed, 10 Aug 2022 11:42:10 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@linux.dev Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nTTKdmMbedBv; Wed, 10 Aug 2022 11:42:08 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 8FC854DACD; Wed, 10 Aug 2022 11:42:08 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A8DE24DACD for ; Wed, 10 Aug 2022 11:42:06 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2himjbY10x6j for ; Wed, 10 Aug 2022 11:42:05 -0400 (EDT) Received: from out2.migadu.com (out2.migadu.com [188.165.223.204]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 74A5B4DACA for ; Wed, 10 Aug 2022 11:42:05 -0400 (EDT) Date: Wed, 10 Aug 2022 10:41:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1660146124; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=K2PbOUqOvValZYHdNM1MGvDbH+NW5HMrQfpzoZhK7ZE=; b=htruQVkH3tRwn67M8lxwDxWJcmqoYYJ7n3o1BU4Nzi+bk/Qkn/2fU9FSTvgictSsmVFw37 cJkohOBnSioV23R1DBb/ZPvkiWp3m9lapoivUmelydT1ZddoDT46WXqNbC/Hyiie9gHtun OW/GmCzkrE0nN2Wx0j9w7JuP90sAbGw= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Subject: Re: [PATCH 5/9] KVM: arm64: PMU: Simplify setting a counter to a specific value Message-ID: References: <20220805135813.2102034-1-maz@kernel.org> <20220805135813.2102034-6-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220805135813.2102034-6-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-Migadu-Auth-User: linux.dev Cc: kvm@vger.kernel.org, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Fri, Aug 05, 2022 at 02:58:09PM +0100, Marc Zyngier wrote: > kvm_pmu_set_counter_value() is pretty odd, as it tries to update > the counter value while taking into account the value that is > currently held by the running perf counter. > > This is not only complicated, this is quite wrong. Nowhere in > the architecture is it said that the counter would be offset > by something that is pending. The counter should be updated > with the value set by SW, and start counting from there if > required. > > Remove the odd computation and just assign the provided value > after having released the perf event (which is then restarted). > > Signed-off-by: Marc Zyngier Looks much better. Reviewed-by: Oliver Upton > --- > arch/arm64/kvm/pmu-emul.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index 9be485d23416..ddd79b64b38a 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -21,6 +21,7 @@ static LIST_HEAD(arm_pmus); > static DEFINE_MUTEX(arm_pmus_lock); > > static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx); > +static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc); > > static u32 kvm_pmu_event_mask(struct kvm *kvm) > { > @@ -129,8 +130,10 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val) > if (!kvm_vcpu_has_pmu(vcpu)) > return; > > + kvm_pmu_release_perf_event(&vcpu->arch.pmu.pmc[select_idx]); > + Not your code, but since we're here: it seems as though there is some inconsistency in parameterization as some functions take an index and others take a kvm_pmc pointer. For example, kvm_pmu_{create,release}_perf_event() are inconsistent. It might be nice to pick a scheme and apply consistently throughout. -- Thanks, Oliver > reg = counter_index_to_reg(select_idx); > - __vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx); > + __vcpu_sys_reg(vcpu, reg) = val; > > /* Recreate the perf event to reflect the updated sample_period */ > kvm_pmu_create_perf_event(vcpu, select_idx); > -- > 2.34.1 > > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37C6EC00140 for ; Wed, 10 Aug 2022 15:43:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bzLxgoBXtx3bnO8+qLwaINgS0GS/nXNQk87wXLg/Itc=; b=bKMFpAcLBaQa4a K2qFlZ3HprYhKd4LXWcv83uRpt+3VY60iAERLukSDfjVl7+C84c0NiknxeBCnS+Py4p/1KPc5iCkL qcJArTke+8fvxkfgQXQWAczz988Tf/mLtBMAS586Yfw8uS4z0Hal/WRqyF4/7FDTfh+SMVEhyFrR4 c4tkcIKPbNZT5iVT863v1VNJPzvmIUC8IfPJ2ObuRPqtNtu97396a1NYGGdfAgIOzujiHsSYo9UP9 8Xrahjwcr73KpBmL1iHVq6M/VAjF/pT6RQuNbVTkv/7VTv9CZ4V6EWyJCvpP/Cyo5uzmJg5LsPqhx b75IgRdgEjkm/4pGTkgg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oLnqf-00CcxZ-Cm; Wed, 10 Aug 2022 15:42:21 +0000 Received: from out2.migadu.com ([188.165.223.204]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oLnqS-00CcuV-NH for linux-arm-kernel@lists.infradead.org; Wed, 10 Aug 2022 15:42:20 +0000 Date: Wed, 10 Aug 2022 10:41:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1660146124; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=K2PbOUqOvValZYHdNM1MGvDbH+NW5HMrQfpzoZhK7ZE=; b=htruQVkH3tRwn67M8lxwDxWJcmqoYYJ7n3o1BU4Nzi+bk/Qkn/2fU9FSTvgictSsmVFw37 cJkohOBnSioV23R1DBb/ZPvkiWp3m9lapoivUmelydT1ZddoDT46WXqNbC/Hyiie9gHtun OW/GmCzkrE0nN2Wx0j9w7JuP90sAbGw= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Ricardo Koller , kernel-team@android.com Subject: Re: [PATCH 5/9] KVM: arm64: PMU: Simplify setting a counter to a specific value Message-ID: References: <20220805135813.2102034-1-maz@kernel.org> <20220805135813.2102034-6-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220805135813.2102034-6-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-Migadu-Auth-User: linux.dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220810_084215_622077_EB56A29D X-CRM114-Status: GOOD ( 24.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 05, 2022 at 02:58:09PM +0100, Marc Zyngier wrote: > kvm_pmu_set_counter_value() is pretty odd, as it tries to update > the counter value while taking into account the value that is > currently held by the running perf counter. > > This is not only complicated, this is quite wrong. Nowhere in > the architecture is it said that the counter would be offset > by something that is pending. The counter should be updated > with the value set by SW, and start counting from there if > required. > > Remove the odd computation and just assign the provided value > after having released the perf event (which is then restarted). > > Signed-off-by: Marc Zyngier Looks much better. Reviewed-by: Oliver Upton > --- > arch/arm64/kvm/pmu-emul.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index 9be485d23416..ddd79b64b38a 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -21,6 +21,7 @@ static LIST_HEAD(arm_pmus); > static DEFINE_MUTEX(arm_pmus_lock); > > static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx); > +static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc); > > static u32 kvm_pmu_event_mask(struct kvm *kvm) > { > @@ -129,8 +130,10 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val) > if (!kvm_vcpu_has_pmu(vcpu)) > return; > > + kvm_pmu_release_perf_event(&vcpu->arch.pmu.pmc[select_idx]); > + Not your code, but since we're here: it seems as though there is some inconsistency in parameterization as some functions take an index and others take a kvm_pmc pointer. For example, kvm_pmu_{create,release}_perf_event() are inconsistent. It might be nice to pick a scheme and apply consistently throughout. -- Thanks, Oliver > reg = counter_index_to_reg(select_idx); > - __vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx); > + __vcpu_sys_reg(vcpu, reg) = val; > > /* Recreate the perf event to reflect the updated sample_period */ > kvm_pmu_create_perf_event(vcpu, select_idx); > -- > 2.34.1 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68D3CC25B07 for ; Wed, 10 Aug 2022 15:42:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230468AbiHJPmL (ORCPT ); Wed, 10 Aug 2022 11:42:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230050AbiHJPmK (ORCPT ); Wed, 10 Aug 2022 11:42:10 -0400 Received: from out2.migadu.com (out2.migadu.com [IPv6:2001:41d0:2:aacc::]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AB9C3B940 for ; Wed, 10 Aug 2022 08:42:06 -0700 (PDT) Date: Wed, 10 Aug 2022 10:41:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1660146124; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=K2PbOUqOvValZYHdNM1MGvDbH+NW5HMrQfpzoZhK7ZE=; b=htruQVkH3tRwn67M8lxwDxWJcmqoYYJ7n3o1BU4Nzi+bk/Qkn/2fU9FSTvgictSsmVFw37 cJkohOBnSioV23R1DBb/ZPvkiWp3m9lapoivUmelydT1ZddoDT46WXqNbC/Hyiie9gHtun OW/GmCzkrE0nN2Wx0j9w7JuP90sAbGw= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Ricardo Koller , kernel-team@android.com Subject: Re: [PATCH 5/9] KVM: arm64: PMU: Simplify setting a counter to a specific value Message-ID: References: <20220805135813.2102034-1-maz@kernel.org> <20220805135813.2102034-6-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220805135813.2102034-6-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-Migadu-Auth-User: linux.dev Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Fri, Aug 05, 2022 at 02:58:09PM +0100, Marc Zyngier wrote: > kvm_pmu_set_counter_value() is pretty odd, as it tries to update > the counter value while taking into account the value that is > currently held by the running perf counter. > > This is not only complicated, this is quite wrong. Nowhere in > the architecture is it said that the counter would be offset > by something that is pending. The counter should be updated > with the value set by SW, and start counting from there if > required. > > Remove the odd computation and just assign the provided value > after having released the perf event (which is then restarted). > > Signed-off-by: Marc Zyngier Looks much better. Reviewed-by: Oliver Upton > --- > arch/arm64/kvm/pmu-emul.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index 9be485d23416..ddd79b64b38a 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -21,6 +21,7 @@ static LIST_HEAD(arm_pmus); > static DEFINE_MUTEX(arm_pmus_lock); > > static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx); > +static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc); > > static u32 kvm_pmu_event_mask(struct kvm *kvm) > { > @@ -129,8 +130,10 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val) > if (!kvm_vcpu_has_pmu(vcpu)) > return; > > + kvm_pmu_release_perf_event(&vcpu->arch.pmu.pmc[select_idx]); > + Not your code, but since we're here: it seems as though there is some inconsistency in parameterization as some functions take an index and others take a kvm_pmc pointer. For example, kvm_pmu_{create,release}_perf_event() are inconsistent. It might be nice to pick a scheme and apply consistently throughout. -- Thanks, Oliver > reg = counter_index_to_reg(select_idx); > - __vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx); > + __vcpu_sys_reg(vcpu, reg) = val; > > /* Recreate the perf event to reflect the updated sample_period */ > kvm_pmu_create_perf_event(vcpu, select_idx); > -- > 2.34.1 > >