Re: [PATCH] RISC-V: Add support fo the zihintpause extension

[Conor Dooley <conor.dooley@microchip.com>]

On Wed, Aug 10, 2022 at 10:33:56PM -0700, Palmer Dabbelt wrote:
> This was recently added to binutils and with any luck will soon be in
> Linux, without it sparse will fail when trying to build new kernels on
> systems with new toolchains.

Replied once already but I am not too familar with mutt and screwed up
the CC list.
Not too keen on the released version of sparse not working during the
merge window, but w/e I'll upgrade my CI manually.

Tested-by: Conor Dooley <conor.dooley@microchip.com>
(with riscv-gnu-toolchain 2022.03.09 & clang-15/LLVM=1)

> 
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> I re-indented the other extensions to match, and this one is on top of
> the Zicbom patch as I figured that'd be easier.
> ---
>  target-riscv.c | 50 +++++++++++++++++++++++++++-----------------------
>  1 file changed, 27 insertions(+), 23 deletions(-)
> 
> diff --git a/target-riscv.c b/target-riscv.c
> index db0f7e57..23d28d0e 100644
> --- a/target-riscv.c
> +++ b/target-riscv.c
> @@ -5,21 +5,22 @@
>  #include <string.h>
>  #include <stdio.h>
>  
> -#define RISCV_32BIT	(1 << 0)
> -#define RISCV_64BIT	(1 << 1)
> -#define RISCV_MUL	(1 << 2)
> -#define RISCV_DIV	(1 << 3)
> -#define RISCV_ATOMIC	(1 << 4)
> -#define RISCV_FLOAT	(1 << 5)
> -#define RISCV_DOUBLE	(1 << 6)
> -#define RISCV_FDIV	(1 << 7)
> -#define RISCV_COMP	(1 << 8)
> -#define RISCV_EMBD	(1 << 9)
> -#define RISCV_FPU	(RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV)
> -#define RISCV_GENERIC	(RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
> -#define RISCV_ZICSR	(1 << 10)
> -#define RISCV_ZIFENCEI	(1 << 11)
> -#define RISCV_ZICBOM	(1 << 12)
> +#define RISCV_32BIT		(1 << 0)
> +#define RISCV_64BIT		(1 << 1)
> +#define RISCV_MUL		(1 << 2)
> +#define RISCV_DIV		(1 << 3)
> +#define RISCV_ATOMIC		(1 << 4)
> +#define RISCV_FLOAT		(1 << 5)
> +#define RISCV_DOUBLE		(1 << 6)
> +#define RISCV_FDIV		(1 << 7)
> +#define RISCV_COMP		(1 << 8)
> +#define RISCV_EMBD		(1 << 9)
> +#define RISCV_FPU		(RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV)
> +#define RISCV_GENERIC		(RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
> +#define RISCV_ZICSR		(1 << 10)
> +#define RISCV_ZIFENCEI		(1 << 11)
> +#define RISCV_ZICBOM		(1 << 12)
> +#define RISCV_ZIHINTPAUSE	(1 << 13)
>  
>  static unsigned int riscv_flags;
>  
> @@ -35,14 +36,15 @@ static void parse_march_riscv(const char *arg)
>  		{ "rv64i",	RISCV_64BIT },
>  		{ "rv64g",	RISCV_64BIT|RISCV_GENERIC },
>  	}, extensions[] = {
> -		{ "m",		RISCV_MUL|RISCV_DIV },
> -		{ "a",		RISCV_ATOMIC },
> -		{ "f",		RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR },
> -		{ "d",		RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR },
> -		{ "c",		RISCV_COMP },
> -		{ "_zicsr",	RISCV_ZICSR },
> -		{ "_zifencei",	RISCV_ZIFENCEI },
> -		{ "_zicbom",	RISCV_ZICBOM },
> +		{ "m",			RISCV_MUL|RISCV_DIV },
> +		{ "a",			RISCV_ATOMIC },
> +		{ "f",			RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR },
> +		{ "d",			RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR },
> +		{ "c",			RISCV_COMP },
> +		{ "_zicsr",		RISCV_ZICSR },
> +		{ "_zifencei",		RISCV_ZIFENCEI },
> +		{ "_zicbom",		RISCV_ZICBOM },
> +		{ "_zihintpause",	RISCV_ZIHINTPAUSE },
>  	};
>  	int i;
>  
> @@ -135,6 +137,8 @@ static void predefine_riscv(const struct target *self)
>  		predefine("__riscv_zifencei", 1, "1");
>  	if (riscv_flags & RISCV_ZICBOM)
>  		predefine("__riscv_zicbom", 1, "1");
> +	if (riscv_flags & RISCV_ZIHINTPAUSE)
> +		predefine("__riscv_zihintpause", 1, "1");
>  
>  	if (cmodel)
>  		predefine_strong("__riscv_cmodel_%s", cmodel);
> -- 
> 2.34.1
>