From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23FD0C32772 for ; Tue, 23 Aug 2022 17:27:48 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 90BBA4CE16; Tue, 23 Aug 2022 13:27:48 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@linux.dev Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VWDkyP4Af3K6; Tue, 23 Aug 2022 13:27:47 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 1A33F4CE19; Tue, 23 Aug 2022 13:27:47 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id D00E84CE14 for ; Tue, 23 Aug 2022 13:27:45 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PVCyHLHRp9j2 for ; Tue, 23 Aug 2022 13:27:44 -0400 (EDT) Received: from out1.migadu.com (out1.migadu.com [91.121.223.63]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 6B8844CE0D for ; Tue, 23 Aug 2022 13:27:44 -0400 (EDT) Date: Tue, 23 Aug 2022 12:27:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1661275662; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=B9cH+rlavh07rmBaYNLiaL07EycjD+h+sDN5b0VRnAk=; b=hLRSAesKGsgS0yM3sd/pZYyle7SguZjXMHnoQy7soEytupF9acck64rtKLWPrTw+gK7y8E FQEmRhf26oI/HRD6hZvVHh+M6wHTSiE/LQSL5cEG3sMuXLD/heahT6F9o8a6nq2POlVbyi tgdEQu2andp3uTGloEdg57fkxmARMN8= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Subject: Re: [PATCH 5/6] KVM: arm64: Treat 32bit ID registers as RAZ/WI on 64bit-only system Message-ID: References: <20220817214818.3243383-1-oliver.upton@linux.dev> <20220817214818.3243383-6-oliver.upton@linux.dev> <87czcqx547.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87czcqx547.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-Migadu-Auth-User: linux.dev Cc: kvm@vger.kernel.org, will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hey Marc, Thanks for the review! On Tue, Aug 23, 2022 at 06:05:28PM +0100, Marc Zyngier wrote: > On Wed, 17 Aug 2022 22:48:17 +0100, > Oliver Upton wrote: > > > > One of the oddities of the architecture is that the AArch64 views of the > > AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any EL. > > Nonetheless, KVM exposes these registers to userspace for the sake of > > save/restore. It is possible that the UNKNOWN value could differ between > > systems, leading to a rejected write from userspace. > > > > Avoid the issue altogether by handling the AArch32 ID registers as > > RAZ/WI when on an AArch64-only system. > > > > Signed-off-by: Oliver Upton > > --- > > arch/arm64/kvm/sys_regs.c | 63 ++++++++++++++++++++++++++------------- > > 1 file changed, 43 insertions(+), 20 deletions(-) > > > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > > index 9f06c85f26b8..5f6a633182c8 100644 > > --- a/arch/arm64/kvm/sys_regs.c > > +++ b/arch/arm64/kvm/sys_regs.c > > @@ -1145,6 +1145,20 @@ static unsigned int id_visibility(const struct kvm_vcpu *vcpu, > > return 0; > > } > > > > +static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, > > + const struct sys_reg_desc *r) > > +{ > > + /* > > + * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any > > + * EL. Promote to RAZ/WI in order to guarantee consistency between > > + * systems. > > + */ > > + if (!kvm_supports_32bit_el0()) > > + return REG_RAZ | REG_USER_WI; > > This is probably only a nit, but why does one visibility has a _USER_ > tag while the other doesn't? In other word, what sysregs are WI from > userspace that aren't so from the guest? > > Also, do we have any cases where RAZ and WI would be used > independently? My gut feeling is that RAZ implies WI in most (all?) > cases. If this assumption holds, shouldn't we simply rename REG_RAZ to > REG_RAZ_WI and be done with it? Yeah, this reads a bit strange, but there is some reason around it (I think!) As it applies to ID registers, REG_RAZ already implies RAZ w/ immutable writes (-EINVAL if something different is written). As such I didn't want to change the meaning of the other ID registers to WI and only ignore writes for the registers that could have an UNKNOWN value. Furthermore, I added the _USER_ tag to make it clear that we aren't magically allowing writes from the guest to these registers. I think we will need an additional visibility bit (or special accessor, which I tried to avoid) to precisely apply WI to the 32bit registers, but if the _USER_ tag is distracting I can get rid of it. After all, hardware should politely UNDEF the guest when writing to such a register. Thoughts? -- Thanks, Oliver _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBE5DC32772 for ; Tue, 23 Aug 2022 17:28:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sRKf8YFoSee7NFNMMXAhx1ijpJm6Em9x4Mmb18c3qYQ=; b=5HAZuo4bYKy25t qE6Ii/P0IKgw0opzZXDqJqijBUSv7BuxBvBCZn8j2hFD01VLvr7aZalaVTHHOE6ldJ1WC5LKd4Qwy wM1NmETHGvbXgm27pZt+4v4hvy/hCPD5SJiqXRRQScdkFZQf1klEZvPi5Te/ylxiHjPjhuaaB5Ue8 J7bGdRseJT0fAGLLFLmB9ka46F+XRBOLe0AEnI78EyFcoVqPUxtQetrYkUjX5ZA42UNzohJjGS7/2 l4tolhUYT3uaxV0wnWTbGC3MelEPwrvgKC9w+q8S/ooHoffIEZCK6AiVqQefXKZA1OBgZwVRr6zXO 08OoaCjkS3htFGHt5X7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQXgv-007iht-2a; Tue, 23 Aug 2022 17:27:53 +0000 Received: from out1.migadu.com ([91.121.223.63]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQXgq-007idg-J0 for linux-arm-kernel@lists.infradead.org; Tue, 23 Aug 2022 17:27:51 +0000 Date: Tue, 23 Aug 2022 12:27:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1661275662; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=B9cH+rlavh07rmBaYNLiaL07EycjD+h+sDN5b0VRnAk=; b=hLRSAesKGsgS0yM3sd/pZYyle7SguZjXMHnoQy7soEytupF9acck64rtKLWPrTw+gK7y8E FQEmRhf26oI/HRD6hZvVHh+M6wHTSiE/LQSL5cEG3sMuXLD/heahT6F9o8a6nq2POlVbyi tgdEQu2andp3uTGloEdg57fkxmARMN8= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, will@kernel.org Subject: Re: [PATCH 5/6] KVM: arm64: Treat 32bit ID registers as RAZ/WI on 64bit-only system Message-ID: References: <20220817214818.3243383-1-oliver.upton@linux.dev> <20220817214818.3243383-6-oliver.upton@linux.dev> <87czcqx547.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87czcqx547.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-Migadu-Auth-User: linux.dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220823_102749_564502_8D06E2EF X-CRM114-Status: GOOD ( 29.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hey Marc, Thanks for the review! On Tue, Aug 23, 2022 at 06:05:28PM +0100, Marc Zyngier wrote: > On Wed, 17 Aug 2022 22:48:17 +0100, > Oliver Upton wrote: > > > > One of the oddities of the architecture is that the AArch64 views of the > > AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any EL. > > Nonetheless, KVM exposes these registers to userspace for the sake of > > save/restore. It is possible that the UNKNOWN value could differ between > > systems, leading to a rejected write from userspace. > > > > Avoid the issue altogether by handling the AArch32 ID registers as > > RAZ/WI when on an AArch64-only system. > > > > Signed-off-by: Oliver Upton > > --- > > arch/arm64/kvm/sys_regs.c | 63 ++++++++++++++++++++++++++------------- > > 1 file changed, 43 insertions(+), 20 deletions(-) > > > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > > index 9f06c85f26b8..5f6a633182c8 100644 > > --- a/arch/arm64/kvm/sys_regs.c > > +++ b/arch/arm64/kvm/sys_regs.c > > @@ -1145,6 +1145,20 @@ static unsigned int id_visibility(const struct kvm_vcpu *vcpu, > > return 0; > > } > > > > +static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, > > + const struct sys_reg_desc *r) > > +{ > > + /* > > + * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any > > + * EL. Promote to RAZ/WI in order to guarantee consistency between > > + * systems. > > + */ > > + if (!kvm_supports_32bit_el0()) > > + return REG_RAZ | REG_USER_WI; > > This is probably only a nit, but why does one visibility has a _USER_ > tag while the other doesn't? In other word, what sysregs are WI from > userspace that aren't so from the guest? > > Also, do we have any cases where RAZ and WI would be used > independently? My gut feeling is that RAZ implies WI in most (all?) > cases. If this assumption holds, shouldn't we simply rename REG_RAZ to > REG_RAZ_WI and be done with it? Yeah, this reads a bit strange, but there is some reason around it (I think!) As it applies to ID registers, REG_RAZ already implies RAZ w/ immutable writes (-EINVAL if something different is written). As such I didn't want to change the meaning of the other ID registers to WI and only ignore writes for the registers that could have an UNKNOWN value. Furthermore, I added the _USER_ tag to make it clear that we aren't magically allowing writes from the guest to these registers. I think we will need an additional visibility bit (or special accessor, which I tried to avoid) to precisely apply WI to the 32bit registers, but if the _USER_ tag is distracting I can get rid of it. After all, hardware should politely UNDEF the guest when writing to such a register. Thoughts? -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1E24C3F6B0 for ; Tue, 23 Aug 2022 19:01:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231454AbiHWTBn (ORCPT ); Tue, 23 Aug 2022 15:01:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233564AbiHWTAZ (ORCPT ); Tue, 23 Aug 2022 15:00:25 -0400 Received: from out1.migadu.com (out1.migadu.com [IPv6:2001:41d0:2:863f::]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BB964A838 for ; Tue, 23 Aug 2022 10:31:11 -0700 (PDT) Date: Tue, 23 Aug 2022 12:27:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1661275662; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=B9cH+rlavh07rmBaYNLiaL07EycjD+h+sDN5b0VRnAk=; b=hLRSAesKGsgS0yM3sd/pZYyle7SguZjXMHnoQy7soEytupF9acck64rtKLWPrTw+gK7y8E FQEmRhf26oI/HRD6hZvVHh+M6wHTSiE/LQSL5cEG3sMuXLD/heahT6F9o8a6nq2POlVbyi tgdEQu2andp3uTGloEdg57fkxmARMN8= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, will@kernel.org Subject: Re: [PATCH 5/6] KVM: arm64: Treat 32bit ID registers as RAZ/WI on 64bit-only system Message-ID: References: <20220817214818.3243383-1-oliver.upton@linux.dev> <20220817214818.3243383-6-oliver.upton@linux.dev> <87czcqx547.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87czcqx547.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-Migadu-Auth-User: linux.dev Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hey Marc, Thanks for the review! On Tue, Aug 23, 2022 at 06:05:28PM +0100, Marc Zyngier wrote: > On Wed, 17 Aug 2022 22:48:17 +0100, > Oliver Upton wrote: > > > > One of the oddities of the architecture is that the AArch64 views of the > > AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any EL. > > Nonetheless, KVM exposes these registers to userspace for the sake of > > save/restore. It is possible that the UNKNOWN value could differ between > > systems, leading to a rejected write from userspace. > > > > Avoid the issue altogether by handling the AArch32 ID registers as > > RAZ/WI when on an AArch64-only system. > > > > Signed-off-by: Oliver Upton > > --- > > arch/arm64/kvm/sys_regs.c | 63 ++++++++++++++++++++++++++------------- > > 1 file changed, 43 insertions(+), 20 deletions(-) > > > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > > index 9f06c85f26b8..5f6a633182c8 100644 > > --- a/arch/arm64/kvm/sys_regs.c > > +++ b/arch/arm64/kvm/sys_regs.c > > @@ -1145,6 +1145,20 @@ static unsigned int id_visibility(const struct kvm_vcpu *vcpu, > > return 0; > > } > > > > +static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, > > + const struct sys_reg_desc *r) > > +{ > > + /* > > + * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any > > + * EL. Promote to RAZ/WI in order to guarantee consistency between > > + * systems. > > + */ > > + if (!kvm_supports_32bit_el0()) > > + return REG_RAZ | REG_USER_WI; > > This is probably only a nit, but why does one visibility has a _USER_ > tag while the other doesn't? In other word, what sysregs are WI from > userspace that aren't so from the guest? > > Also, do we have any cases where RAZ and WI would be used > independently? My gut feeling is that RAZ implies WI in most (all?) > cases. If this assumption holds, shouldn't we simply rename REG_RAZ to > REG_RAZ_WI and be done with it? Yeah, this reads a bit strange, but there is some reason around it (I think!) As it applies to ID registers, REG_RAZ already implies RAZ w/ immutable writes (-EINVAL if something different is written). As such I didn't want to change the meaning of the other ID registers to WI and only ignore writes for the registers that could have an UNKNOWN value. Furthermore, I added the _USER_ tag to make it clear that we aren't magically allowing writes from the guest to these registers. I think we will need an additional visibility bit (or special accessor, which I tried to avoid) to precisely apply WI to the 32bit registers, but if the _USER_ tag is distracting I can get rid of it. After all, hardware should politely UNDEF the guest when writing to such a register. Thoughts? -- Thanks, Oliver