From: Stefan Hajnoczi <stefanha@redhat.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, alistair23@gmail.com
Subject: Re: [PULL 00/44] riscv-to-apply queue
Date: Wed, 7 Sep 2022 09:53:30 -0400 [thread overview]
Message-ID: <YxiiWiCTc6rQlCdE@fedora> (raw)
In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com>
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.
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next prev parent reply other threads:[~2022-09-07 13:55 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-07 8:03 [PULL 00/44] riscv-to-apply queue Alistair Francis via
2022-09-07 8:03 ` [PULL 01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Alistair Francis via
2022-09-07 8:03 ` [PULL 02/44] target/riscv: Force disable extensions if priv spec version does not match Alistair Francis via
2022-09-07 8:03 ` [PULL 03/44] target/riscv: fix shifts shamt value for rv128c Alistair Francis via
2022-09-07 8:03 ` [PULL 04/44] target/riscv: move zmmul out of the experimental properties Alistair Francis via
2022-09-07 8:03 ` [PULL 05/44] hw/riscv: virt: pass random seed to fdt Alistair Francis via
2022-09-07 8:03 ` [PULL 06/44] target/riscv: Add check for supported privilege mode combinations Alistair Francis via
2022-09-07 8:03 ` [PULL 07/44] target/riscv: H extension depends on I extension Alistair Francis via
2022-09-07 8:03 ` [PULL 08/44] target/riscv: Fix checkpatch warning may triggered in csr_ops table Alistair Francis via
2022-09-07 8:03 ` [PULL 09/44] target/riscv: Add check for csrs existed with U extension Alistair Francis via
2022-09-07 8:03 ` [PULL 10/44] target/riscv: Fix checks in hmode/hmode32 Alistair Francis via
2022-09-07 8:03 ` [PULL 11/44] target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check Alistair Francis via
2022-09-07 8:03 ` [PULL 12/44] roms/opensbi: Upgrade from v1.0 to v1.1 Alistair Francis via
2022-09-07 8:03 ` [PULL 13/44] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V Alistair Francis via
2022-09-07 8:03 ` [PULL 14/44] docs: List kvm as a supported accelerator on RISC-V Alistair Francis via
2022-09-07 8:03 ` [PULL 15/44] target/riscv: rvv: Add mask agnostic for vv instructions Alistair Francis via
2022-09-07 8:03 ` [PULL 16/44] target/riscv: rvv: Add mask agnostic for vector load / store instructions Alistair Francis via
2022-09-07 8:03 ` [PULL 17/44] target/riscv: rvv: Add mask agnostic for vx instructions Alistair Francis via
2022-09-07 8:03 ` [PULL 18/44] target/riscv: rvv: Add mask agnostic for vector integer shift instructions Alistair Francis via
2022-09-07 8:03 ` [PULL 19/44] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions Alistair Francis via
2022-09-07 8:03 ` [PULL 20/44] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions Alistair Francis via
2022-09-07 8:03 ` [PULL 21/44] target/riscv: rvv: Add mask agnostic for vector floating-point instructions Alistair Francis via
2022-09-07 8:03 ` [PULL 22/44] target/riscv: rvv: Add mask agnostic for vector mask instructions Alistair Francis via
2022-09-07 8:03 ` [PULL 23/44] target/riscv: rvv: Add mask agnostic for vector permutation instructions Alistair Francis via
2022-09-07 8:03 ` [PULL 24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior Alistair Francis via
2022-09-07 8:03 ` [PULL 25/44] target/riscv: Add Zihintpause support Alistair Francis via
2022-09-07 8:03 ` [PULL 26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() Alistair Francis via
2022-09-07 8:03 ` [PULL 27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check Alistair Francis via
2022-09-07 8:03 ` [PULL 28/44] hw/riscv: opentitan: bump opentitan version Alistair Francis via
2022-09-07 8:03 ` [PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals Alistair Francis via
2022-09-07 8:03 ` [PULL 30/44] target/riscv: Remove additional priv version check for mcountinhibit Alistair Francis via
2022-09-07 8:03 ` [PULL 31/44] hw/riscv: virt: fix uart node name Alistair Francis via
2022-09-07 8:03 ` [PULL 32/44] hw/riscv: virt: fix the plic's address cells Alistair Francis via
2022-09-07 8:03 ` [PULL 33/44] hw/riscv: virt: fix syscon subnode paths Alistair Francis via
2022-09-07 8:03 ` [PULL 34/44] hw/core: fix platform bus node name Alistair Francis via
2022-09-07 8:03 ` [PULL 35/44] target/riscv: Add xicondops in ISA entry Alistair Francis via
2022-09-07 8:03 ` [PULL 36/44] target/riscv: Use official extension names for AIA CSRs Alistair Francis via
2022-09-07 8:03 ` [PULL 37/44] hw/intc: Move mtimer/mtimecmp to aclint Alistair Francis via
2022-09-07 8:03 ` [PULL 38/44] target/riscv: Add stimecmp support Alistair Francis via
2022-09-07 8:03 ` [PULL 39/44] target/riscv: Add vstimecmp support Alistair Francis via
2022-09-07 8:03 ` [PULL 40/44] target/riscv: Add sscofpmf extension support Alistair Francis via
2022-09-07 8:03 ` [PULL 41/44] target/riscv: Simplify counter predicate function Alistair Francis via
2022-09-07 8:03 ` [PULL 42/44] target/riscv: Add few cache related PMU events Alistair Francis via
2022-09-07 8:03 ` [PULL 43/44] hw/riscv: virt: Add PMU DT node to the device tree Alistair Francis via
2022-09-07 8:03 ` [PULL 44/44] target/riscv: Update the privilege field for sscofpmf CSRs Alistair Francis via
2022-09-07 13:53 ` Stefan Hajnoczi [this message]
2022-09-07 14:18 ` [PULL 00/44] riscv-to-apply queue Stefan Hajnoczi
2022-09-08 8:12 ` Alistair Francis
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