Re: [PATCH] arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()

From: Catalin Marinas <catalin.marinas@arm.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Will Deacon <will@kernel.org>, Christoph Hellwig <hch@lst.de>,
	linux-arm-kernel@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Ard Biesheuvel <ardb@kernel.org>
Subject: Re: [PATCH] arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()
Date: Thu, 8 Sep 2022 14:27:19 +0100	[thread overview]
Message-ID: <Yxntt+VbVh+xau2L@arm.com> (raw)
In-Reply-To: <Yxnn1QhhLf/2ROrq@arm.com>

On Thu, Sep 08, 2022 at 02:02:13PM +0100, Catalin Marinas wrote:
> On Thu, Sep 08, 2022 at 12:32:42PM +0100, Robin Murphy wrote:
> > On 2022-09-08 11:32, Catalin Marinas wrote:
> > > The architecture requires invalidate or clean while also stating that
> > > clean+invalidate can be used instead, so I don't think there's much to
> > > justify. From the mismatched attributes section:
> > > 
> > > 1. If the mismatched attributes for a memory location all assign the
> > >     same shareability attribute to a Location that has a cacheable
> > >     attribute,
> > 
> > This is not describing our case, though. We do have a cacheable attribute in
> > at least one alias, but the shareability is *not* the same across all
> > aliases, therefore at face value it clearly does not apply.
> 
> From the CPU perspective, both the cacheable and non-cacheable aliases
> have the same inner shareable attribute. The device accessing the buffer
> presumably should use the same shareability attributes. In the worst
> case it's outer shareable but on most implementations the inner and
> outer shareability domains are the same.

Ah, so you are referring to this paragraph:

  The shareability field is only relevant if the memory is a Normal
  Cacheable memory type. All Device and Normal Non-cacheable memory
  regions are always treated as Outer Shareable, regardless of the
  translation table shareability attributes.

I think so far we've ignored this case and I'm not aware hardware that
would break coherency here. There's a theoretical risk that some system
level cache only resides in the outer shareable domain and any cache
maintenance on the inner shareable alias does not affect it. IIRC we
have another case where the architecture requires the inner and outer
shareable domains to be the same (a fairly recent update w.r.t. FWB). We
could ask the architects to clarify the mismatched aliases to include
the outer vs inner case here.

But if you want the same attributes, we can change the Linux linear
mapping to outer shareable.

-- 
Catalin

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel