All of lore.kernel.org
 help / color / mirror / Atom feed
From: Andi Shyti <andi.shyti@linux.intel.com>
To: "Gupta, Anshuman" <anshuman.gupta@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Auld, Matthew" <matthew.auld@intel.com>,
	"Vivi, Rodrigo" <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm
Date: Wed, 14 Sep 2022 17:35:44 +0200	[thread overview]
Message-ID: <YyH00K6oxqwlyWu9@alfio.lan> (raw)
In-Reply-To: <CY5PR11MB6211B3178019DC4309DE43CB95469@CY5PR11MB6211.namprd11.prod.outlook.com>

Hi Anshuman,

[...]

> > > > +	 *  which really disables the PCIe power savings and leaves the bridge to
> > D0
> > > > +	 *  state.
> > > > +	 *  Let's disable i915 rpm till we fix all known issue with lmem access in
> > D3.
> > > > +	 */
> > > > +	.has_runtime_pm = 0,
> > > >  };
> > > >
> > > >  static const struct intel_device_info adl_s_info = { @@ -1076,6
> > > > +1096,7 @@ static const struct intel_device_info dg2_info = {
> > > >  	XE_LPD_FEATURES,
> > > >  	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) |
> > BIT(TRANSCODER_B) |
> > > >  			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> > > > +	.has_runtime_pm = 0,
> > >
> > > The FIXME msg can be smaller, but it also needs to be here.
> > 
> > I actually like the comment, is very clear and helps understanding the issue :)
> Shall I move the comment to commit log , and keep a smaller comment for both DG1 and DG2 ?
> With that I can address your comment and Rodrigo comment as well.
> Keeping such a big comment at two places will not make any sense.

OK for me!

Thanks!
Andi

  reply	other threads:[~2022-09-14 15:35 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-14 14:15 [Intel-gfx] [PATCH] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm Anshuman Gupta
2022-09-14 14:33 ` Rodrigo Vivi
2022-09-14 14:43   ` Andi Shyti
2022-09-14 14:50     ` Gupta, Anshuman
2022-09-14 15:35       ` Andi Shyti [this message]
2022-09-14 15:43 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2) Patchwork
2022-09-14 16:05   ` Gupta, Anshuman
2022-09-14 16:09     ` Gupta, Anshuman
2022-09-14 16:34       ` Vudum, Lakshminarayana
2022-09-14 16:13 ` [Intel-gfx] [PATCH v2] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm Anshuman Gupta
2022-09-15  6:47   ` Joonas Lahtinen
2022-09-15  7:19     ` Gupta, Anshuman
2022-09-15 14:44   ` Joonas Lahtinen
2022-09-14 16:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2) Patchwork
2022-09-14 17:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev3) Patchwork
2022-09-15  9:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2022-09-13  7:32 [Intel-gfx] [PATCH] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm Anshuman Gupta

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YyH00K6oxqwlyWu9@alfio.lan \
    --to=andi.shyti@linux.intel.com \
    --cc=anshuman.gupta@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=matthew.auld@intel.com \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.