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d="scan'208";a="572115814" Received: from yangzhon.bj.intel.com (HELO yangzhon) ([10.238.157.60]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 00:44:49 -0700 Date: Mon, 26 Sep 2022 03:42:11 -0400 From: Yang Zhong To: Xiaoyao Li Cc: "Dr. David Alan Gilbert" , "Wang, Lei" , paul.c.lai@intel.com, pbonzini@redhat.com, qemu-devel@nongnu.org, robert.hu@intel.com, chenyi.qiang@intel.com, yang.zhong@linux.intel.com Subject: Re: [PATCH] i386: Add new CPU model SapphireRapids Message-ID: References: <20220812055751.14553-1-lei4.wang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: none client-ip=192.55.52.120; envelope-from=yang.zhong@linux.intel.com; helo=mga04.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sat, Sep 24, 2022 at 12:01:16AM +0800, Xiaoyao Li wrote: > On 9/23/2022 9:30 PM, Yang Zhong wrote: > > On Wed, Sep 21, 2022 at 03:51:42PM +0100, Dr. David Alan Gilbert wrote: > > > * Wang, Lei (lei4.wang@intel.com) wrote: > > > > The new CPU model mostly inherits features from Icelake-Server, while > > > > adding new features: > > > > - AMX (Advance Matrix eXtensions) > > > > - Bus Lock Debug Exception > > > > and new instructions: > > > > - AVX VNNI (Vector Neural Network Instruction): > > > > - VPDPBUS: Multiply and Add Unsigned and Signed Bytes > > > > - VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation > > > > - VPDPWSSD: Multiply and Add Signed Word Integers > > > > - VPDPWSSDS: Multiply and Add Signed Integers with Saturation > > > > - FP16: Replicates existing AVX512 computational SP (FP32) instructions > > > > using FP16 instead of FP32 for ~2X performance gain > > > > - SERIALIZE: Provide software with a simple way to force the processor to > > > > complete all modifications, faster, allowed in all privilege levels and > > > > not causing an unconditional VM exit > > > > - TSX Suspend Load Address Tracking: Allows programmers to choose which > > > > memory accesses do not need to be tracked in the TSX read set > > > > - AVX512_BF16: Vector Neural Network Instructions supporting BFLOAT16 > > > > inputs and conversion instructions from IEEE single precision > > > > > > > > Features may be added in future versions: > > > > - CET (virtualization support hasn't been merged) > > > > Instructions may be added in future versions: > > > > - fast zero-length MOVSB (KVM doesn't support yet) > > > > - fast short STOSB (KVM doesn't support yet) > > > > - fast short CMPSB, SCASB (KVM doesn't support yet) > > > > > > > > Signed-off-by: Wang, Lei > > > > Reviewed-by: Robert Hoo > > > > > > Hi, > > > What fills in the AMX tile and tmul information leafs > > > (0x1D, 0x1E)? > > > In particular, how would we make sure when we migrate between two > > > generations of AMX/Tile/Tmul capable devices with different > > > register/palette/tmul limits that the migration is tied to the CPU type > > > correctly? > > > Would you expect all devices called a 'SappireRapids' to have the same > > > sizes? > > > > > > > There is only one palette in current design. This palette include 8 > > tiles. Those two CPUID leafs defined bytes_per_tile, total_tile_bytes, > > max_rows and etc, the AMX tool will configure those values into TILECFG with > > ldtilecfg instrcutions. Once tiles are configured, we can use > > tileload instruction to load data into those tiles. > > > > We did migration between two SappireRapids with amx self test tool > > (tools/testing/selftests/x86/amx.c)started in two sides, the migration > > work well. > > > > As for SappireRapids and more newer cpu types, those two CPUID leafs > > definitions are all same on AMX. > > I'm not sure what definitions mean here. Are you saying the CPUID values of > leaf 0x1D and 0x1E won't change for any future Intel Silicion? > > Personally, I doubt it. And we shouldn't take such assumption unless Intel > states it SDM. The current 0x1D and 0x1E definitions as below: /* CPUID Leaf 0x1D constants: */ #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 #define INTEL_AMX_BYTES_PER_TILE 0x400 #define INTEL_AMX_BYTES_PER_ROW 0x40 #define INTEL_AMX_TILE_MAX_NAMES 0x8 #define INTEL_AMX_TILE_MAX_ROWS 0x10 /* CPUID Leaf 0x1E constants: */ #define INTEL_AMX_TMUL_MAX_K 0x10 #define INTEL_AMX_TMUL_MAX_N 0x40 These values are defined from SDM, and from the new developping CPU, these values are still same with SappireRapids. thanks! Yang > > > So, on AMX perspective, the migration > > should be workable on subsequent cpu types. thanks! > > I think what Dave worried is that when migrating one VM created with > "SapphireRapids" model on SPR machine to some newer platform in the future, > where the newer platform reports different value on CPUID leaves 0x1D and > 0x1E than SPR platform. > > I think we need to contain CPUID leaves 0x1D and 0x1E into CPU model as > well. Otherwise we will hit the same as Intel PT that SPR reports less > capabilities that ICX. >