From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matthew Auld <matthew.auld@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Nirmoy Das <nirmoy.das@intel.com>,
Jianshui Yu <jianshui.yu@intel.com>
Subject: Re: [Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers
Date: Tue, 4 Oct 2022 16:39:39 +0300 [thread overview]
Message-ID: <Yzw3m1lUeSMl0Q1S@intel.com> (raw)
In-Reply-To: <20221004131916.233474-4-matthew.auld@intel.com>
On Tue, Oct 04, 2022 at 02:19:15PM +0100, Matthew Auld wrote:
> For these types of display buffers, we need to able to CPU access some
> part of the backing memory in prepare_plane_clear_colors(). As a result
> we need to ensure we always place in the mappable part of lmem, which
> becomes necessary on small-bar systems.
>
> v2(Nirmoy & Ville):
> - Add some commentary for why we need to CPU access the buffer.
> - Split out the other changes, so we just consider the display change
> here.
> v3:
> - Handle this in the dpt path.
> v4(Ville):
> - Drop the intel_fb_rc_ccs_cc_plane() sanity check in
> pin_and_fence_fb_obj(), since we can also trigger this on DG1 it
> seems.
On some hw I think there was also a chicken bit to disable DPT,
and the DPT simulation situation was always a mess (you had
to enable it using some custom config). So in theory someone
might have the need to use the non-DPT path on more modern hw
as well, but I'm OK not considering it here. If someone thinks
that small-bar+no-DPT is important they can deal with it in a
separate patch.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Fixes: eb1c535f0d69 ("drm/i915: turn on small BAR support")
> Reported-by: Jianshui Yu <jianshui.yu@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fb_pin.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> index 5031ee5695dd..e12339f46640 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> @@ -50,7 +50,18 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
> continue;
>
> if (HAS_LMEM(dev_priv)) {
> - ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0);
> + unsigned int flags = obj->flags;
> +
> + /*
> + * For this type of buffer we need to able to read from the CPU
> + * the clear color value found in the buffer, hence we need to
> + * ensure it is always in the mappable part of lmem, if this is
> + * a small-bar device.
> + */
> + if (intel_fb_rc_ccs_cc_plane(fb) >= 0)
> + flags &= ~I915_BO_ALLOC_GPU_ONLY;
> + ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0,
> + flags);
> if (ret)
> continue;
> }
> --
> 2.37.3
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2022-10-04 13:39 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-04 13:19 [Intel-gfx] [PATCH v5 1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj Matthew Auld
2022-10-04 13:19 ` [Intel-gfx] [PATCH v5 2/5] drm/i915/display: handle migration for dpt Matthew Auld
2022-10-04 13:31 ` Ville Syrjälä
2022-10-04 13:19 ` [Intel-gfx] [PATCH v5 3/5] drm/i915: allow control over the flags when migrating Matthew Auld
2022-10-04 13:19 ` [Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers Matthew Auld
2022-10-04 13:39 ` Ville Syrjälä [this message]
2022-10-04 13:40 ` Das, Nirmoy
2022-10-11 13:54 ` Tvrtko Ursulin
2022-10-11 14:39 ` Matthew Auld
2022-10-11 15:03 ` Tvrtko Ursulin
2022-10-11 15:28 ` Matthew Auld
2022-10-11 16:35 ` Tvrtko Ursulin
2022-10-04 13:19 ` [Intel-gfx] [PATCH v5 5/5] drm/i915: check memory is mappable in read_from_page Matthew Auld
2022-10-04 19:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj Patchwork
2022-10-04 19:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-04 19:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-05 5:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-10-04 10:51 [Intel-gfx] [PATCH v5 1/5] " Matthew Auld
2022-10-04 10:51 ` [Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers Matthew Auld
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