From: Chao Gao <chao.gao@intel.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>
Cc: <linux-kernel@vger.kernel.org>, <x86@kernel.org>,
<tglx@linutronix.de>, <mingo@redhat.com>, <bp@alien8.de>,
<dave.hansen@linux.intel.com>, <colinmitchell@google.com>
Subject: Re: [PATCH v2a 3/6] x86/microcode/intel: Establish staging control logic
Date: Wed, 26 Mar 2025 15:35:25 +0800 [thread overview]
Message-ID: <Z+OuPbNGC6mOCHZ1@intel.com> (raw)
In-Reply-To: <20250321211853.13909-1-chang.seok.bae@intel.com>
>+static void stage_microcode(void)
>+{
>+ unsigned int pkg_id = UINT_MAX;
>+ enum ucode_state ret;
>+ u64 mmio_pa;
>+ int cpu;
>+
>+ if (!IS_ALIGNED(get_totalsize(&ucode_patch_late->hdr), sizeof(u32)))
>+ return;
>+
>+ lockdep_assert_cpus_held();
>+
>+ /*
>+ * The MMIO address is unique per package, and all the SMT
>+ * primary threads are online here. Find each MMIO space by
>+ * their package ids to avoid duplicate staging.
>+ */
>+ for_each_cpu(cpu, cpu_online_mask) {
for_each_online_cpu(cpu)?
>+ if (!topology_is_primary_thread(cpu) ||
>+ topology_logical_package_id(cpu) == pkg_id)
>+ continue;
Documentation/arch/x86/topology.rst states:
- topology_core_cpumask():
The cpumask contains all online threads in the package to which a thread
belongs.
The number of online threads is also printed in /proc/cpuinfo "siblings."
So, how about:
if (cpu != cpumask_first(topology_core_cpumask(cpu)))
continue;
and dropping the pkg_id?
>+ pkg_id = topology_logical_package_id(cpu);
>+
>+ rdmsrl_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &mmio_pa);
Note rdmsrl_on_cpu() may return an error. please consider adding
error-handling. Is it possible that somehow one package doesn't support
this staging feature while others do?
>+
>+ ret = do_stage(mmio_pa);
>+ if (ret != UCODE_OK) {
>+ pr_err("Error: staging failed with %s for CPU%d at package %u.\n",
>+ ret == UCODE_TIMEOUT ? "timeout" : "error state",
>+ cpu, pkg_id);
Shall we print a message somewhere showing "Continuing updates without
staging"?
It could be confusing for users to see a success message following an error
message that states "Error: staging failed ..."
>+ return;
>+ }
>+ }
>+
>+ pr_info("Staging of patch revision 0x%x succeeded.\n",
>+ ((struct microcode_header_intel *)ucode_patch_late)->rev);
>+}
>+
> static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci,
> struct microcode_intel *mc,
> u32 *cur_rev)
>@@ -648,6 +696,7 @@ static struct microcode_ops microcode_intel_ops = {
> .collect_cpu_info = collect_cpu_info,
> .apply_microcode = apply_microcode_late,
> .finalize_late_load = finalize_late_load,
>+ .stage_microcode = stage_microcode,
> .use_nmi = IS_ENABLED(CONFIG_X86_64),
> };
>
>--
>2.45.2
>
next prev parent reply other threads:[~2025-03-26 7:36 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-20 23:40 [PATCH v2 0/6] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 1/6] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 2/6] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 3/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-03-21 21:18 ` [PATCH v2a " Chang S. Bae
2025-03-26 7:35 ` Chao Gao [this message]
2025-03-26 18:43 ` Chang S. Bae
2025-03-27 1:44 ` Chao Gao
2025-03-28 14:12 ` Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 4/6] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-03-21 0:15 ` Dave Hansen
2025-03-21 21:19 ` [PATCH v2a " Chang S. Bae
2025-03-26 8:34 ` Chao Gao
2025-03-26 18:43 ` Chang S. Bae
2025-03-21 21:19 ` [PATCH v2 " Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 5/6] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-03-21 21:19 ` [PATCH v2a " Chang S. Bae
2025-03-27 3:32 ` [PATCH v2 " Chao Gao
2025-03-27 14:11 ` Chang S. Bae
2025-03-31 19:16 ` Dave Hansen
2025-03-20 23:40 ` [PATCH v2 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 0/6] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 1/6] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 2/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 3/6] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 4/6] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 5/6] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-04-16 14:14 ` Chao Gao
2025-04-16 17:22 ` Chang S. Bae
2025-04-16 17:37 ` Dave Hansen
2025-04-09 23:27 ` [PATCH v3 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 0/6] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 1/6] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-08-18 7:45 ` Chao Gao
2025-08-13 17:26 ` [PATCH v4 2/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-08-13 18:21 ` Dave Hansen
2025-08-13 20:46 ` Chang S. Bae
2025-08-13 20:55 ` Dave Hansen
2025-08-14 18:30 ` Chang S. Bae
2025-08-22 22:39 ` [PATCH] x86/cpu/topology: Make primary thread mask available with SMP=n Chang S. Bae
2025-08-23 16:05 ` Chang S. Bae
2025-08-22 22:39 ` [PATCH v4a 2/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-08-22 23:34 ` Dave Hansen
2025-08-13 17:26 ` [PATCH v4 3/6] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-08-13 18:25 ` Dave Hansen
2025-08-22 22:39 ` [PATCH v4a " Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 4/6] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-08-13 18:44 ` Dave Hansen
2025-08-22 22:39 ` [PATCH v4a " Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 5/6] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-08-13 19:07 ` Dave Hansen
2025-08-22 22:40 ` [PATCH v4a " Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-08-18 8:35 ` Chao Gao
2025-08-22 22:42 ` Chang S. Bae
2025-08-13 19:08 ` [PATCH v4 0/6] x86: Support for Intel Microcode Staging Feature Dave Hansen
2025-08-23 15:52 ` [PATCH v5 0/7] " Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 1/7] x86/cpu/topology: Make primary thread mask available with SMP=n Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 2/7] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-09-04 12:08 ` Borislav Petkov
2025-09-05 0:06 ` Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 3/7] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-09-04 12:13 ` Borislav Petkov
2025-09-05 0:04 ` Chang S. Bae
2025-09-05 11:13 ` Borislav Petkov
2025-09-05 16:31 ` Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 4/7] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-09-04 13:48 ` Borislav Petkov
2025-09-05 0:05 ` Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 5/7] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-09-10 18:33 ` Borislav Petkov
2025-09-10 21:31 ` Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 6/7] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-09-12 16:34 ` Borislav Petkov
2025-09-13 0:51 ` Chang S. Bae
2025-09-13 19:01 ` Borislav Petkov
2025-08-23 15:52 ` [PATCH v5 7/7] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-08-26 22:13 ` [PATCH v5 0/7] x86: Support for Intel Microcode Staging Feature Luck, Tony
2025-08-26 22:15 ` Chang S. Bae
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