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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
	jani.nikula@linux.intel.com,
	mitulkumar.ajitkumar.golani@intel.com
Subject: Re: [PATCH 2/2] drm/i915/display: Avoid use of VTOTAL.Vtotal bits
Date: Wed, 26 Mar 2025 15:35:10 +0200	[thread overview]
Message-ID: <Z-QCjqVlEpVVaJ3z@intel.com> (raw)
In-Reply-To: <20250326040538.504861-3-ankit.k.nautiyal@intel.com>

On Wed, Mar 26, 2025 at 09:35:38AM +0530, Ankit Nautiyal wrote:
> For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> bits are not required. Since the support for these bits is going to
> be deprecated in upcoming platforms, avoid writing these bits for the
> platforms that do not use legacy Timing Generator.
> 
> Since for these platforms TRAN_VMIN is always filled with crtc_vtotal,
> use TRAN_VRR_VMIN to get the vtotal for adjusted_mode.
> 
> v2: Avoid having a helper for manipulating VTOTAL register, and instead
> just make the change where required. (Ville)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 41 ++++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_vrr.c     | 15 +++++--
>  2 files changed, 50 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bde53b2de70c..37e27dcfda05 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2639,6 +2639,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> +	u32 vtotal_bits;
>  	int vsyncshift = 0;
>  
>  	drm_WARN_ON(display->drm, !transcoder_has_vrr(cpu_transcoder));
> @@ -2695,9 +2696,21 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
>  		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>  
> +	/*
> +	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> +	 * bits are not required. Since the support for these bits is going to
> +	 * be deprecated in upcoming platforms, avoid writing these bits for the
> +	 * platforms that do not use legacy Timing Generator.
> +	 */
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		vtotal_bits = 0;

I think just setting crtc_vtotal=1 here (like we do for crtc_vblank_start)
would take care of this without the need for extra variables.


> +	else
> +		vtotal_bits = VTOTAL(crtc_vtotal - 1);
> +
>  	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
>  		       VACTIVE(crtc_vdisplay - 1) |
> -		       VTOTAL(crtc_vtotal - 1));
> +		       vtotal_bits);
> +
>  	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
>  		       VBLANK_START(crtc_vblank_start - 1) |
>  		       VBLANK_END(crtc_vblank_end - 1));
> @@ -2722,6 +2735,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> +	u32 vtotal_bits;
>  
>  	drm_WARN_ON(display->drm, !transcoder_has_vrr(cpu_transcoder));
>  
> @@ -2755,13 +2769,24 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>  	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
>  		       VBLANK_START(crtc_vblank_start - 1) |
>  		       VBLANK_END(crtc_vblank_end - 1));
> +	/*
> +	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> +	 * bits are not required. Since the support for these bits is going to
> +	 * be deprecated in upcoming platforms, avoid writing these bits for the
> +	 * platforms that do not use legacy Timing Generator.
> +	 */
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		vtotal_bits = 0;
> +	else
> +		vtotal_bits = VTOTAL(crtc_vtotal - 1);
> +
>  	/*
>  	 * The double buffer latch point for TRANS_VTOTAL
>  	 * is the transcoder's undelayed vblank.
>  	 */
>  	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
>  		       VACTIVE(crtc_vdisplay - 1) |
> -		       VTOTAL(crtc_vtotal - 1));
> +		       vtotal_bits);
>  
>  	intel_vrr_set_fixed_rr_timings(crtc_state);
>  	intel_vrr_transcoder_enable(crtc_state);
> @@ -2824,7 +2849,17 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  
>  	tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
>  	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
> -	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
> +
> +	/*
> +	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> +	 * bits are not filled. The value for adjusted_mode->crtc_vtotal is read
> +	 * from VRR_VMIN register in intel_vrr_get_config.
> +	 * Just set this to 0 here.
> +	 */
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		adjusted_mode->crtc_vtotal = 0;
> +	else
> +		adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
>  
>  	/* FIXME TGL+ DSI transcoders have this! */
>  	if (!transcoder_is_dsi(cpu_transcoder)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 414f93851059..cace1d7c99d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -674,9 +674,19 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -	u32 trans_vrr_ctl, trans_vrr_vsync;
> +	u32 trans_vrr_ctl, trans_vrr_vsync, trans_vrr_vmin;
>  	bool vrr_enable;
>  
> +	/*
> +	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> +	 * bits are not filled. Since for these platforms TRAN_VMIN is always
> +	 * filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for
> +	 * adjusted_mode.
> +	 */
> +	trans_vrr_vmin = intel_de_read(display, TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		crtc_state->hw.adjusted_mode.crtc_vtotal = trans_vrr_vmin;

I think this should rather use intel_vrr_vmin_vtotal(), and for
reason it needs to be near the end so thaI guess for that
reason it has to be done after the actual vmin readout.

> +
>  	trans_vrr_ctl = intel_de_read(display,
>  				      TRANS_VRR_CTL(display, cpu_transcoder));
>  
> @@ -705,8 +715,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  							 TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
>  		crtc_state->vrr.vmax = intel_de_read(display,
>  						     TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;
> -		crtc_state->vrr.vmin = intel_de_read(display,
> -						     TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
> +		crtc_state->vrr.vmin = trans_vrr_vmin;
>  
>  		if (HAS_AS_SDP(display)) {
>  			trans_vrr_vsync =
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2025-03-26 13:35 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-26  4:05 [PATCH 0/2] VRR Register Read/Write Updates Ankit Nautiyal
2025-03-26  4:05 ` [PATCH 1/2] drm/i915/display: Introduce transcoder_has_vrr() helper Ankit Nautiyal
2025-03-26 13:01   ` Ville Syrjälä
2025-03-26  4:05 ` [PATCH 2/2] drm/i915/display: Avoid use of VTOTAL.Vtotal bits Ankit Nautiyal
2025-03-26 13:35   ` Ville Syrjälä [this message]
2025-03-26  4:23 ` ✓ CI.Patch_applied: success for VRR Register Read/Write Updates Patchwork
2025-03-26  4:23 ` ✓ CI.checkpatch: " Patchwork
2025-03-26  4:24 ` ✓ CI.KUnit: " Patchwork
2025-03-26  4:40 ` ✓ CI.Build: " Patchwork
2025-03-26  4:44 ` ✓ CI.Hooks: " Patchwork
2025-03-26  4:45 ` ✓ CI.checksparse: " Patchwork
2025-03-26  5:06 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-03-26  6:11 ` ✓ i915.CI.BAT: success " Patchwork
2025-03-26  8:52 ` ✗ i915.CI.Full: failure " Patchwork
2025-03-26 17:49 ` ✗ Xe.CI.Full: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2025-03-26 16:03 [PATCH 0/2] " Ankit Nautiyal
2025-03-26 16:03 ` [PATCH 2/2] drm/i915/display: Avoid use of VTOTAL.Vtotal bits Ankit Nautiyal
2025-03-26 17:09   ` Ville Syrjälä
2025-03-27  4:35     ` Nautiyal, Ankit K
2025-03-27 14:46 [PATCH 0/2] VRR Register Read/Write Updates Ankit Nautiyal
2025-03-27 14:46 ` [PATCH 2/2] drm/i915/display: Avoid use of VTOTAL.Vtotal bits Ankit Nautiyal
2025-03-28 10:36   ` Ville Syrjälä

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