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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b79e311sm11484777f8f.78.2025.03.31.07.12.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Mar 2025 07:12:26 -0700 (PDT) Date: Mon, 31 Mar 2025 15:12:26 +0100 From: Stafford Horne To: kernel test robot Cc: Sahil Siddiq , oe-kbuild-all@lists.linux.dev Subject: Re: [linux-next:master 13940/14141] arch/openrisc/include/asm/spr.h:16:27: error: impossible constraint in 'asm' Message-ID: References: <202503311807.BZaUHY5L-lkp@intel.com> Precedence: bulk X-Mailing-List: oe-kbuild-all@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <202503311807.BZaUHY5L-lkp@intel.com> On Mon, Mar 31, 2025 at 07:05:53PM +0800, kernel test robot wrote: > tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master > head: 405e2241def89c88f008dcb899eb5b6d4be8b43c > commit: c5c6fd8be51207f0abd3e5a6ed4fd5220b0bdecd [13940/14141] openrisc: Introduce new utility functions to flush and invalidate caches > config: openrisc-randconfig-r062-20250331 (https://download.01.org/0day-ci/archive/20250331/202503311807.BZaUHY5L-lkp@intel.com/config) > compiler: or1k-linux-gcc (GCC) 13.3.0 > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250331/202503311807.BZaUHY5L-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot > | Closes: https://lore.kernel.org/oe-kbuild-all/202503311807.BZaUHY5L-lkp@intel.com/ > > All error/warnings (new ones prefixed by >>): > > In file included from arch/openrisc/mm/cache.c:13: > In function 'cache_loop', > inlined from 'cache_loop_page' at arch/openrisc/mm/cache.c:51:2: > >> arch/openrisc/include/asm/spr.h:16:27: warning: 'asm' operand 0 probably does not match constraints > 16 | #define mtspr(_spr, _val) __asm__ __volatile__ ( \ > | ^~~~~~~ > arch/openrisc/mm/cache.c:38:17: note: in expansion of macro 'mtspr' > 38 | mtspr(reg, paddr); > | ^~~~~ > >> arch/openrisc/include/asm/spr.h:16:27: error: impossible constraint in 'asm' > 16 | #define mtspr(_spr, _val) __asm__ __volatile__ ( \ > | ^~~~~~~ > arch/openrisc/mm/cache.c:38:17: note: in expansion of macro 'mtspr' > 38 | mtspr(reg, paddr); > | ^~~~~ Hi Suhil, This is due to reg being defined as usigned int in the new cache functions. It should used short as the SPR_* regs are limited to 16-bit addresses. Could you fix this and resend? I tried to recreate this with gcc 14.2.0 and make W=1 but didn't manage to get the same error. So pleae check if you can reproduce too and fix any other warnings there may be. -Stafford > > vim +/asm +16 arch/openrisc/include/asm/spr.h > > 58e0166a4772aa Jonas Bonn 2011-06-04 15 > 58e0166a4772aa Jonas Bonn 2011-06-04 @16 #define mtspr(_spr, _val) __asm__ __volatile__ ( \ > 58e0166a4772aa Jonas Bonn 2011-06-04 17 "l.mtspr r0,%1,%0" \ > 58e0166a4772aa Jonas Bonn 2011-06-04 18 : : "K" (_spr), "r" (_val)) > 58e0166a4772aa Jonas Bonn 2011-06-04 19 #define mtspr_off(_spr, _off, _val) __asm__ __volatile__ ( \ > 58e0166a4772aa Jonas Bonn 2011-06-04 20 "l.mtspr %0,%1,%2" \ > 58e0166a4772aa Jonas Bonn 2011-06-04 21 : : "r" (_off), "r" (_val), "K" (_spr)) > 58e0166a4772aa Jonas Bonn 2011-06-04 22 > > :::::: The code at line 16 was first introduced by commit > :::::: 58e0166a4772aaeb10c9b0f6d59f19099d2047df OpenRISC: Headers > > :::::: TO: Jonas Bonn > :::::: CC: Jonas Bonn > > -- > 0-DAY CI Kernel Test Service > https://github.com/intel/lkp-tests/wiki