From: Ingo Molnar <mingo@kernel.org>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: "Xin Li (Intel)" <xin@zytor.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev,
linux-edac@vger.kernel.org, kvm@vger.kernel.org,
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linux-pm@vger.kernel.org, bpf@vger.kernel.org,
llvm@lists.linux.dev, tglx@linutronix.de, mingo@redhat.com,
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jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org,
acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com,
alexander.shishkin@linux.intel.com, jolsa@kernel.org,
irogers@google.com, adrian.hunter@intel.com,
kan.liang@linux.intel.com, wei.liu@kernel.org,
ajay.kaher@broadcom.com, alexey.amakhalov@broadcom.com,
bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com,
pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com,
luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com,
haiyangz@microsoft.com, decui@microsoft.com,
Linus Torvalds <torvalds@linux-foundation.org>
Subject: Re: [RFC PATCH v1 01/15] x86/msr: Replace __wrmsr() with native_wrmsrl()
Date: Tue, 1 Apr 2025 09:52:52 +0200 [thread overview]
Message-ID: <Z-ubVFyoOzwKhI53@gmail.com> (raw)
In-Reply-To: <9D15DE81-2E68-4FCD-A133-4963602E18C9@zytor.com>
* H. Peter Anvin <hpa@zytor.com> wrote:
> On March 31, 2025 3:17:30 AM PDT, Ingo Molnar <mingo@kernel.org> wrote:
> >
> >* Xin Li (Intel) <xin@zytor.com> wrote:
> >
> >> - __wrmsr (MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3, val >> 32);
> >> + native_wrmsrl(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3);
> >
> >This is an improvement.
> >
> >> - __wrmsr (MSR_IA32_PQR_ASSOC, rmid_p, plr->closid);
> >> + native_wrmsrl(MSR_IA32_PQR_ASSOC, (u64)plr->closid << 32 | rmid_p);
> >
> >> - __wrmsr (MSR_IA32_PQR_ASSOC, rmid_p, closid_p);
> >> + native_wrmsrl(MSR_IA32_PQR_ASSOC, (u64)closid_p << 32 | rmid_p);
> >
> >This is not an improvement.
> >
> >Please provide a native_wrmsrl() API variant where natural [rmid_p, closid_p]
> >high/lo parameters can be used, without the shift-uglification...
> >
> >Thanks,
> >
> > Ingo
>
> Directing this question primarily to Ingo, who is more than anyone
> else the namespace consistency guardian:
>
> On the subject of msr function naming ... *msrl() has always been
> misleading. The -l suffix usually means 32 bits; sometimes it means
> the C type "long" (which in the kernel is used instead of
> size_t/uintptr_t, which might end up being "fun" when 128-bit
> architectures appear some time this century), but for a fixed 64-but
> type we normally use -q.
Yeah, agreed - that's been bothering me for a while too. :-)
> Should we rename the *msrl() functions to *msrq() as part of this
> overhaul?
Yeah, that's a good idea, and because talk is cheap I just implemented
this in the tip:WIP.x86/msr branch with a couple of other cleanups in
this area (see the shortlog & diffstat below), but the churn is high:
144 files changed, 1034 insertions(+), 1034 deletions(-)
So this can only be done if regenerated and sent to Linus right before
an -rc1 I think:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip WIP.x86/msr
Thanks,
Ingo
=======================>
Ingo Molnar (18):
x86/msr: Standardize on u64 in <asm/msr.h>
x86/msr: Standardize on u64 in <asm/msr-index.h>
x86/msr: Use u64 in rdmsrl_amd_safe() and wrmsrl_amd_safe()
x86/msr: Use u64 in rdmsrl_safe() and paravirt_read_pmc()
x86/msr: Rename 'rdmsrl()' to 'rdmsrq()'
x86/msr: Rename 'wrmsrl()' to 'wrmsrq()'
x86/msr: Rename 'rdmsrl_safe()' to 'rdmsrq_safe()'
x86/msr: Rename 'wrmsrl_safe()' to 'wrmsrq_safe()'
x86/msr: Rename 'rdmsrl_safe_on_cpu()' to 'rdmsrq_safe_on_cpu()'
x86/msr: Rename 'wrmsrl_safe_on_cpu()' to 'wrmsrq_safe_on_cpu()'
x86/msr: Rename 'rdmsrl_on_cpu()' to 'rdmsrq_on_cpu()'
x86/msr: Rename 'wrmsrl_on_cpu()' to 'wrmsrq_on_cpu()'
x86/msr: Rename 'mce_rdmsrl()' to 'mce_rdmsrq()'
x86/msr: Rename 'mce_wrmsrl()' to 'mce_wrmsrq()'
x86/msr: Rename 'rdmsrl_amd_safe()' to 'rdmsrq_amd_safe()'
x86/msr: Rename 'wrmsrl_amd_safe()' to 'wrmsrq_amd_safe()'
x86/msr: Rename 'native_wrmsrl()' to 'native_wrmsrq()'
x86/msr: Rename 'wrmsrl_cstar()' to 'wrmsrq_cstar()'
arch/x86/coco/sev/core.c | 2 +-
arch/x86/events/amd/brs.c | 8 +-
arch/x86/events/amd/core.c | 12 +--
arch/x86/events/amd/ibs.c | 26 ++---
arch/x86/events/amd/lbr.c | 20 ++--
arch/x86/events/amd/power.c | 10 +-
arch/x86/events/amd/uncore.c | 12 +--
arch/x86/events/core.c | 42 ++++----
arch/x86/events/intel/core.c | 66 ++++++-------
arch/x86/events/intel/cstate.c | 2 +-
arch/x86/events/intel/ds.c | 10 +-
arch/x86/events/intel/knc.c | 16 +--
arch/x86/events/intel/lbr.c | 44 ++++-----
arch/x86/events/intel/p4.c | 24 ++---
arch/x86/events/intel/p6.c | 12 +--
arch/x86/events/intel/pt.c | 32 +++---
arch/x86/events/intel/uncore.c | 2 +-
arch/x86/events/intel/uncore_discovery.c | 10 +-
arch/x86/events/intel/uncore_nhmex.c | 70 ++++++-------
arch/x86/events/intel/uncore_snb.c | 42 ++++----
arch/x86/events/intel/uncore_snbep.c | 50 +++++-----
arch/x86/events/msr.c | 2 +-
arch/x86/events/perf_event.h | 26 ++---
arch/x86/events/probe.c | 2 +-
arch/x86/events/rapl.c | 8 +-
arch/x86/events/zhaoxin/core.c | 16 +--
arch/x86/hyperv/hv_apic.c | 4 +-
arch/x86/hyperv/hv_init.c | 66 ++++++-------
arch/x86/hyperv/hv_spinlock.c | 6 +-
arch/x86/hyperv/ivm.c | 2 +-
arch/x86/include/asm/apic.h | 8 +-
arch/x86/include/asm/debugreg.h | 4 +-
arch/x86/include/asm/fsgsbase.h | 4 +-
arch/x86/include/asm/kvm_host.h | 2 +-
arch/x86/include/asm/microcode.h | 2 +-
arch/x86/include/asm/msr-index.h | 12 +--
arch/x86/include/asm/msr.h | 50 +++++-----
arch/x86/include/asm/paravirt.h | 8 +-
arch/x86/include/asm/spec-ctrl.h | 2 +-
arch/x86/kernel/acpi/cppc.c | 8 +-
arch/x86/kernel/amd_nb.c | 2 +-
arch/x86/kernel/apic/apic.c | 16 +--
arch/x86/kernel/apic/apic_numachip.c | 6 +-
arch/x86/kernel/cet.c | 2 +-
arch/x86/kernel/cpu/amd.c | 28 +++---
arch/x86/kernel/cpu/aperfmperf.c | 28 +++---
arch/x86/kernel/cpu/bugs.c | 24 ++---
arch/x86/kernel/cpu/bus_lock.c | 18 ++--
arch/x86/kernel/cpu/common.c | 68 ++++++-------
arch/x86/kernel/cpu/feat_ctl.c | 4 +-
arch/x86/kernel/cpu/hygon.c | 6 +-
arch/x86/kernel/cpu/intel.c | 10 +-
arch/x86/kernel/cpu/intel_epb.c | 12 +--
arch/x86/kernel/cpu/mce/amd.c | 22 ++---
arch/x86/kernel/cpu/mce/core.c | 58 +++++------
arch/x86/kernel/cpu/mce/inject.c | 32 +++---
arch/x86/kernel/cpu/mce/intel.c | 32 +++---
arch/x86/kernel/cpu/mce/internal.h | 2 +-
arch/x86/kernel/cpu/microcode/amd.c | 2 +-
arch/x86/kernel/cpu/microcode/intel.c | 2 +-
arch/x86/kernel/cpu/mshyperv.c | 12 +--
arch/x86/kernel/cpu/resctrl/core.c | 10 +-
arch/x86/kernel/cpu/resctrl/monitor.c | 2 +-
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 2 +-
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 6 +-
arch/x86/kernel/cpu/sgx/main.c | 2 +-
arch/x86/kernel/cpu/topology.c | 2 +-
arch/x86/kernel/cpu/topology_amd.c | 4 +-
arch/x86/kernel/cpu/tsx.c | 20 ++--
arch/x86/kernel/cpu/umwait.c | 2 +-
arch/x86/kernel/fpu/core.c | 2 +-
arch/x86/kernel/fpu/xstate.c | 10 +-
arch/x86/kernel/fpu/xstate.h | 2 +-
arch/x86/kernel/fred.c | 20 ++--
arch/x86/kernel/hpet.c | 2 +-
arch/x86/kernel/kvm.c | 28 +++---
arch/x86/kernel/kvmclock.c | 4 +-
arch/x86/kernel/mmconf-fam10h_64.c | 8 +-
arch/x86/kernel/process.c | 16 +--
arch/x86/kernel/process_64.c | 20 ++--
arch/x86/kernel/reboot_fixups_32.c | 2 +-
arch/x86/kernel/shstk.c | 18 ++--
arch/x86/kernel/traps.c | 10 +-
arch/x86/kernel/tsc.c | 2 +-
arch/x86/kernel/tsc_sync.c | 14 +--
arch/x86/kvm/svm/avic.c | 2 +-
arch/x86/kvm/svm/sev.c | 2 +-
arch/x86/kvm/svm/svm.c | 16 +--
arch/x86/kvm/vmx/nested.c | 4 +-
arch/x86/kvm/vmx/pmu_intel.c | 4 +-
arch/x86/kvm/vmx/sgx.c | 8 +-
arch/x86/kvm/vmx/vmx.c | 66 ++++++-------
arch/x86/kvm/x86.c | 38 ++++----
arch/x86/lib/insn-eval.c | 6 +-
arch/x86/lib/msr-smp.c | 16 +--
arch/x86/lib/msr.c | 4 +-
arch/x86/mm/pat/memtype.c | 4 +-
arch/x86/mm/tlb.c | 2 +-
arch/x86/pci/amd_bus.c | 10 +-
arch/x86/platform/olpc/olpc-xo1-rtc.c | 6 +-
arch/x86/platform/olpc/olpc-xo1-sci.c | 2 +-
arch/x86/power/cpu.c | 26 ++---
arch/x86/realmode/init.c | 2 +-
arch/x86/virt/svm/sev.c | 20 ++--
arch/x86/xen/suspend.c | 6 +-
drivers/acpi/acpi_extlog.c | 2 +-
drivers/acpi/acpi_lpit.c | 2 +-
drivers/cpufreq/acpi-cpufreq.c | 8 +-
drivers/cpufreq/amd-pstate-ut.c | 6 +-
drivers/cpufreq/amd-pstate.c | 22 ++---
drivers/cpufreq/amd_freq_sensitivity.c | 2 +-
drivers/cpufreq/e_powersaver.c | 6 +-
drivers/cpufreq/intel_pstate.c | 108 ++++++++++-----------
drivers/cpufreq/longhaul.c | 24 ++---
drivers/cpufreq/powernow-k7.c | 14 +--
drivers/crypto/ccp/sev-dev.c | 2 +-
drivers/edac/amd64_edac.c | 6 +-
drivers/gpu/drm/i915/selftests/librapl.c | 4 +-
drivers/hwmon/fam15h_power.c | 6 +-
drivers/idle/intel_idle.c | 34 +++----
drivers/mtd/nand/raw/cs553x_nand.c | 6 +-
drivers/platform/x86/intel/ifs/core.c | 4 +-
drivers/platform/x86/intel/ifs/load.c | 20 ++--
drivers/platform/x86/intel/ifs/runtest.c | 16 +--
drivers/platform/x86/intel/pmc/cnp.c | 6 +-
drivers/platform/x86/intel/pmc/core.c | 8 +-
.../x86/intel/speed_select_if/isst_if_common.c | 18 ++--
.../x86/intel/speed_select_if/isst_if_mbox_msr.c | 14 +--
.../x86/intel/speed_select_if/isst_tpmi_core.c | 2 +-
drivers/platform/x86/intel/tpmi_power_domains.c | 4 +-
drivers/platform/x86/intel/turbo_max_3.c | 4 +-
.../x86/intel/uncore-frequency/uncore-frequency.c | 10 +-
drivers/platform/x86/intel_ips.c | 36 +++----
drivers/powercap/intel_rapl_msr.c | 6 +-
.../int340x_thermal/processor_thermal_device.c | 2 +-
drivers/thermal/intel/intel_hfi.c | 14 +--
drivers/thermal/intel/intel_powerclamp.c | 4 +-
drivers/thermal/intel/intel_tcc_cooling.c | 4 +-
drivers/thermal/intel/therm_throt.c | 10 +-
drivers/video/fbdev/geode/gxfb_core.c | 2 +-
drivers/video/fbdev/geode/lxfb_ops.c | 22 ++---
drivers/video/fbdev/geode/suspend_gx.c | 10 +-
drivers/video/fbdev/geode/video_gx.c | 16 +--
include/hyperv/hvgdk_mini.h | 2 +-
144 files changed, 1034 insertions(+), 1034 deletions(-)
next prev parent reply other threads:[~2025-04-01 7:53 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-31 8:22 [RFC PATCH v1 00/15] MSR refactor with new MSR instructions support Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 01/15] x86/msr: Replace __wrmsr() with native_wrmsrl() Xin Li (Intel)
2025-03-31 10:17 ` Ingo Molnar
2025-03-31 20:32 ` H. Peter Anvin
2025-04-01 5:53 ` Xin Li
2025-04-02 15:41 ` Dave Hansen
2025-04-02 15:56 ` H. Peter Anvin
2025-04-09 19:53 ` Ingo Molnar
2025-04-09 19:56 ` Dave Hansen
2025-04-09 20:11 ` Ingo Molnar
2025-04-01 7:52 ` Ingo Molnar [this message]
2025-04-02 3:45 ` Xin Li
2025-04-02 4:10 ` Ingo Molnar
2025-04-02 4:57 ` Xin Li
2025-04-08 17:34 ` Xin Li
2025-04-03 5:09 ` Xin Li
2025-04-03 6:01 ` H. Peter Anvin
2025-04-09 19:17 ` [PATCH] x86/msr: Standardize on 'u32' MSR indices in <asm/msr.h> Ingo Molnar
2025-03-31 21:45 ` [RFC PATCH v1 01/15] x86/msr: Replace __wrmsr() with native_wrmsrl() Andrew Cooper
2025-04-01 5:13 ` H. Peter Anvin
2025-04-01 5:29 ` Xin Li
2025-04-03 7:13 ` Xin Li
2025-03-31 8:22 ` [RFC PATCH v1 02/15] x86/msr: Replace __rdmsr() with native_rdmsrl() Xin Li (Intel)
2025-03-31 10:26 ` Ingo Molnar
2025-03-31 8:22 ` [RFC PATCH v1 03/15] x86/msr: Simplify pmu_msr_{read,write}() Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 04/15] x86/msr: Let pv_cpu_ops.write_msr{_safe}() take an u64 instead of two u32 Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 05/15] x86/msr: Replace wrmsr(msr, low, 0) with wrmsrl(msr, value) Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 06/15] x86/msr: Remove MSR write APIs that take the MSR value in two u32 arguments Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 07/15] x86/msr: Remove pmu_msr_{read,write}() Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 08/15] x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 09/15] x86/opcode: Add immediate form MSR instructions to x86-opcode-map Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 10/15] KVM: VMX: Use WRMSRNS or its immediate form when available Xin Li (Intel)
2025-03-31 20:27 ` Konrad Rzeszutek Wilk
2025-03-31 20:38 ` Borislav Petkov
2025-03-31 20:41 ` Andrew Cooper
2025-03-31 20:55 ` H. Peter Anvin
2025-03-31 20:45 ` H. Peter Anvin
2025-04-10 23:24 ` Sean Christopherson
2025-04-11 16:18 ` Xin Li
2025-04-11 20:50 ` H. Peter Anvin
2025-04-12 4:28 ` Xin Li
2025-04-11 21:12 ` Jim Mattson
2025-04-12 4:32 ` Xin Li
2025-04-12 23:10 ` H. Peter Anvin
2025-04-14 17:48 ` Xin Li
2025-04-15 6:56 ` H. Peter Anvin
2025-04-15 17:06 ` Xin Li
2025-04-15 17:07 ` H. Peter Anvin
2025-03-31 8:22 ` [RFC PATCH v1 11/15] x86/extable: Implement EX_TYPE_FUNC_REWIND Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 12/15] x86/msr: Use the alternatives mechanism to write MSR Xin Li (Intel)
2025-04-01 22:50 ` kernel test robot
2025-03-31 8:22 ` [RFC PATCH v1 13/15] x86/msr: Use the alternatives mechanism to read MSR Xin Li (Intel)
2025-04-14 17:13 ` Francesco Lavra
2025-04-17 11:10 ` Xin Li
2025-03-31 8:22 ` [RFC PATCH v1 14/15] x86/extable: Add support for the immediate form MSR instructions Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 15/15] x86/msr: Move the ARGS macros after the MSR read/write APIs Xin Li (Intel)
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