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Wed, 27 Nov 2024 00:44:19 -0800 (PST) Date: Wed, 27 Nov 2024 09:44:18 +0100 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Javi Merino Cc: xen-devel@lists.xenproject.org, Jan Beulich , Andrew Cooper Subject: Re: [XEN PATCH v1] x86/APIC: Read Error Status Register correctly Message-ID: References: <3270b77c005745dcf56cc833bdf3e4c703190b05.1732639041.git.javi.merino@cloud.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3270b77c005745dcf56cc833bdf3e4c703190b05.1732639041.git.javi.merino@cloud.com> On Tue, Nov 26, 2024 at 05:06:15PM +0000, Javi Merino wrote: > The logic to read the APIC_ESR was copied from linux in a commit from > 2002: 4676bbf96dc8 (bitkeeper revision > 1.2 (3ddb79c9KusG02eh7i-uXkgY0IksKA), 2002-11-20). In linux 3.14, > this logic was fixed to follow the Intel SDM (see commit > 60283df7ac26 (x86/apic: Read Error Status Register correctly, > 2014-01-14) in the linux kernel). The Intel(r) 64 and IA-32 > Architectures Software Develover's Manual currently says > in Volume 3, Section 12.5.3: > > Before attempt to read from the ESR, software should first write to > it. (The value written does not affect the values read subsequently; > only zero may be written in x2APIC mode.) This write clears any > previously logged errors and updates the ESR with any errors > detected since the last write to the ESR. This write also rearms the > APIC error interrupt triggering mechanism. > > Update error_interrupt() to remove the first read and follow the Intel > manual. > > Signed-off-by: Javi Merino Acked-by: Roger Pau Monné Not sure whether the plan is to squash your commit and Andrews. Thanks, Roger.